ROM_CTRL/64KB Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.760s 736.794us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.260s 3.703ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.450s 289.973us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.200s 391.043us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.080s 547.041us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.910s 312.531us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.450s 289.973us 1 1 100.00
rom_ctrl_csr_aliasing 7.080s 547.041us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.920s 747.625us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.760s 383.318us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.050s 1.049ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 27.830s 20.100ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 16.740s 1.061ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.950s 1.068ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.760s 1.053ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.760s 1.053ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.260s 3.703ms 1 1 100.00
rom_ctrl_csr_rw 7.450s 289.973us 1 1 100.00
rom_ctrl_csr_aliasing 7.080s 547.041us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.900s 590.407us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.260s 3.703ms 1 1 100.00
rom_ctrl_csr_rw 7.450s 289.973us 1 1 100.00
rom_ctrl_csr_aliasing 7.080s 547.041us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.900s 590.407us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 53.490s 1.205ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 21.200s 3.328ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.629m 2.706ms 1 1 100.00
rom_ctrl_tl_intg_err 36.100s 2.108ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.629m 2.706ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.629m 2.706ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 53.490s 1.205ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 53.490s 1.205ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 53.490s 1.205ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 53.490s 1.205ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 53.490s 1.205ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.629m 2.706ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.629m 2.706ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.760s 736.794us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.760s 736.794us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.760s 736.794us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 36.100s 2.108ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 53.490s 1.205ms 1 1 100.00
rom_ctrl_kmac_err_chk 16.740s 1.061ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 53.490s 1.205ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 53.490s 1.205ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 53.490s 1.205ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 21.200s 3.328ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.629m 2.706ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.079m 19.056ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00