RV_DM/USE_JTAG_INTERFACE Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.670s 2.968ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.070s 1.220ms 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.700s 318.321us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 6.900s 4.929ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.470s 1.164ms 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 23.560s 18.753ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 6.350s 3.122ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 27.660s 14.956ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.227m 35.591ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.710s 634.479us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.130s 570.866us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.880s 468.615us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.880s 716.896us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.760s 131.626us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.620s 1.274ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.620s 60.765us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.140s 1.003ms 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.710s 634.479us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.900s 189.833us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.840s 318.014us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.880s 468.615us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.850s 105.663us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.440s 195.361us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.250s 220.683us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 19.360s 3.119ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 42.780s 4.785ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.680s 26.698us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 42.780s 4.785ms 1 1 100.00
rv_dm_csr_rw 2.250s 220.683us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.520s 35.186us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.630s 27.303us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 2.670s 2.968ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.590s 253.960us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.970s 118.613us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 2.430s 505.690us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.220s 385.989us 1 1 100.00
V2 sba rv_dm_sba_tl_access 4.270s 4.675ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.720s 241.738us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 5.450s 8.517ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.550s 367.759us 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.780s 807.596us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.830s 642.858us 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.950s 261.816us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.900s 386.639us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 6.250s 8.075ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.680s 38.910us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.570s 85.000us 1 1 100.00
V2 stress_all rv_dm_stress_all 6.510s 2.696ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.530s 107.806us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.690s 72.696us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.690s 72.696us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 42.780s 4.785ms 1 1 100.00
rv_dm_csr_hw_reset 2.440s 195.361us 1 1 100.00
rv_dm_csr_rw 2.250s 220.683us 1 1 100.00
rv_dm_same_csr_outstanding 6.640s 2.249ms 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 42.780s 4.785ms 1 1 100.00
rv_dm_csr_hw_reset 2.440s 195.361us 1 1 100.00
rv_dm_csr_rw 2.250s 220.683us 1 1 100.00
rv_dm_same_csr_outstanding 6.640s 2.249ms 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 2.350s 512.066us 1 1 100.00
rv_dm_tl_intg_err 12.960s 1.471ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 12.960s 1.471ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.830s 642.858us 1 1 100.00
rv_dm_debug_disabled 1.830s 92.044us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.830s 642.858us 1 1 100.00
rv_dm_debug_disabled 1.830s 92.044us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 2.670s 2.968ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.160s 397.055us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.600s 117.698us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.600s 117.698us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.160s 397.055us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.570s 97.390us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.520s 37.794us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets