RV_TIMER Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.540s	30.382us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.610s	42.476us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.530s	32.136us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.690s	435.284us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.890s	37.317us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.850s	23.164us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.530s	32.136us	1	1	100.00
		rv_timer_csr_aliasing	1.890s	37.317us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.660s	855.541us	1	1	100.00
V2	disabled	rv_timer_disabled	2.980s	2.728ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	7.406m	2.328s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	7.406m	2.328s	1	1	100.00
V2	stress	rv_timer_stress_all	2.640s	2.529ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.530s	35.356us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.440s	55.947us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.930s	130.907us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.930s	130.907us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.610s	42.476us	1	1	100.00
		rv_timer_csr_rw	1.530s	32.136us	1	1	100.00
		rv_timer_csr_aliasing	1.890s	37.317us	1	1	100.00
		rv_timer_same_csr_outstanding	1.440s	18.019us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.610s	42.476us	1	1	100.00
		rv_timer_csr_rw	1.530s	32.136us	1	1	100.00
		rv_timer_csr_aliasing	1.890s	37.317us	1	1	100.00
		rv_timer_same_csr_outstanding	1.440s	18.019us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.990s	328.182us	1	1	100.00
		rv_timer_tl_intg_err	1.880s	90.883us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.880s	90.883us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	31.070s	47.670ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.510s	11.937us	1	1	100.00
		rv_timer_max	1.540s	49.265us	1	1	100.00
		TOTAL			19	19	100.00