SPI_DEVICE/1R1W Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.038m	91.175ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.800s	26.151us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.270s	29.060us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.580s	786.592us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.600s	653.714us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.070s	206.994us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.270s	29.060us	1	1	100.00
		spi_device_csr_aliasing	11.600s	653.714us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.540s	11.822us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.740s	130.923us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.600s	17.552us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.620s	1.251us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.750s	1.775us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.570s	65.828us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.570s	65.828us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.690s	10.168ms	1	1	100.00
		spi_device_tpm_sts_read	1.670s	104.409us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.650s	3.763ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.330s	21.628ms	1	1	100.00
		spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	8.210s	1.534ms	1	1	100.00
		spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	8.210s	1.534ms	1	1	100.00
		spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.670s	202.199us	1	1	100.00
		spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.670s	202.199us	1	1	100.00
		spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.670s	202.199us	1	1	100.00
		spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.670s	202.199us	1	1	100.00
		spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.670s	202.199us	1	1	100.00
		spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	20.650s	9.182ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.140s	560.045us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.140s	560.045us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.140s	560.045us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.530s	929.037us	1	1	100.00
		spi_device_read_buffer_direct	5.160s	259.008us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.140s	560.045us	1	1	100.00
		spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	5.482m	81.205ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.170s	1.204ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.170s	1.204ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.038m	91.175ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	38.610s	10.421ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.803m	57.121ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.690s	16.479us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.630s	13.290us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.880s	362.087us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.880s	362.087us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.800s	26.151us	1	1	100.00
		spi_device_csr_rw	2.270s	29.060us	1	1	100.00
		spi_device_csr_aliasing	11.600s	653.714us	1	1	100.00
		spi_device_same_csr_outstanding	3.510s	230.566us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.800s	26.151us	1	1	100.00
		spi_device_csr_rw	2.270s	29.060us	1	1	100.00
		spi_device_csr_aliasing	11.600s	653.714us	1	1	100.00
		spi_device_same_csr_outstanding	3.510s	230.566us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.020s	165.472us	1	1	100.00
		spi_device_tl_intg_err	16.430s	3.309ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.430s	3.309ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	37.310s	9.089ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.62795823023898520145954593066374979303389950927860651335917509949816717560291
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    940988 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[31])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    940988 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    940988 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[927])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.24667647043327884250118828568757843469154761840956094881361481503010463003397
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1036441 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1036441 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1099441 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbbc573 [101110111100010101110011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1099441 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xbbc573 [101110111100010101110011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])