SPI_DEVICE/2P Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.074m	9.075ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.960s	124.274us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.440s	164.893us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.000s	3.210ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.760s	3.918ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.940s	56.072us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.440s	164.893us	1	1	100.00
		spi_device_csr_aliasing	15.760s	3.918ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.650s	12.230us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.150s	36.734us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.840s	213.753us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.930s	53.877us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.700s	1.649us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.440s	46.364us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.440s	46.364us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.430s	717.850us	1	1	100.00
		spi_device_tpm_sts_read	1.830s	132.280us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.970s	14.487us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.910s	37.994us	1	1	100.00
		spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	19.370s	9.959ms	1	1	100.00
		spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	19.370s	9.959ms	1	1	100.00
		spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.080s	768.354us	1	1	100.00
		spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.080s	768.354us	1	1	100.00
		spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.080s	768.354us	1	1	100.00
		spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.080s	768.354us	1	1	100.00
		spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.080s	768.354us	1	1	100.00
		spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	22.690s	11.209ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.750s	248.796us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.750s	248.796us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.750s	248.796us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	33.170s	12.001ms	1	1	100.00
		spi_device_read_buffer_direct	4.610s	1.040ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.750s	248.796us	1	1	100.00
		spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.016m	84.694ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.790s	271.365us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.790s	271.365us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.074m	9.075ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.492m	40.486ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.970s	51.506us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.670s	15.918us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.470s	16.215us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.430s	244.965us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.430s	244.965us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.960s	124.274us	1	1	100.00
		spi_device_csr_rw	2.440s	164.893us	1	1	100.00
		spi_device_csr_aliasing	15.760s	3.918ms	1	1	100.00
		spi_device_same_csr_outstanding	3.120s	53.880us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.960s	124.274us	1	1	100.00
		spi_device_csr_rw	2.440s	164.893us	1	1	100.00
		spi_device_csr_aliasing	15.760s	3.918ms	1	1	100.00
		spi_device_same_csr_outstanding	3.120s	53.880us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	1.870s	102.881us	1	1	100.00
		spi_device_tl_intg_err	13.360s	2.158ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.360s	2.158ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.130s	984.687us	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.31959543186587398241841883504114825906141696646862767459096512319698086634880
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    793904 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    793904 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    825904 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0xbb0b69 [101110110000101101101001] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    825904 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)