SPI_HOST Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	39.000s	17.191ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	20.286us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	37.107us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	619.165us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	70.469us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	39.428us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	37.107us	1	1	100.00
		spi_host_csr_aliasing	4.000s	70.469us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	19.244us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	48.891us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	5.000s	63.731us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	130.683us	1	1	100.00
		spi_host_error_cmd	4.000s	26.632us	1	1	100.00
		spi_host_event	30.000s	991.373us	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	83.105us	1	1	100.00
V2	speed	spi_host_speed	5.000s	83.105us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	83.105us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	7.000s	191.161us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	30.110us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	83.105us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	83.105us	1	1	100.00
V2	duplex	spi_host_smoke	39.000s	17.191ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	39.000s	17.191ms	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	97.884us	1	1	100.00
V2	spien	spi_host_spien	4.000s	185.689us	1	1	100.00
V2	stall	spi_host_status_stall	1.033m	8.568ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	6.000s	507.279us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	130.683us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	16.873us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	29.639us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	296.225us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	296.225us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	20.286us	1	1	100.00
		spi_host_csr_rw	4.000s	37.107us	1	1	100.00
		spi_host_csr_aliasing	4.000s	70.469us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	58.430us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	20.286us	1	1	100.00
		spi_host_csr_rw	4.000s	37.107us	1	1	100.00
		spi_host_csr_aliasing	4.000s	70.469us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	58.430us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	56.713us	1	1	100.00
		spi_host_sec_cm	3.000s	80.693us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	56.713us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.150m	23.762ms	1	1	100.00
		TOTAL			26	26	100.00