SRAM_CTRL/MAIN Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	37.840s	3.580ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.680s	52.365us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.670s	15.110us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.640s	85.096us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.750s	45.652us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.800s	371.311us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.670s	15.110us	1	1	100.00
		sram_ctrl_csr_aliasing	1.750s	45.652us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.204m	20.691ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	48.090s	1.030ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.686m	7.793ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.890m	6.750ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	10.518m	55.962ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	14.090s	4.297ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	35.150s	10.510ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.547m	25.309ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.000s	1.162ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.180m	5.315ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	37.170s	1.991ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	17.580s	766.944us	1	1	100.00
		sram_ctrl_throughput_w_readback	16.200s	3.355ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.133m	10.021ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.270s	355.078us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	47.181m	129.822ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.800s	125.931us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.570s	161.520us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.570s	161.520us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.680s	52.365us	1	1	100.00
		sram_ctrl_csr_rw	1.670s	15.110us	1	1	100.00
		sram_ctrl_csr_aliasing	1.750s	45.652us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	30.741us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.680s	52.365us	1	1	100.00
		sram_ctrl_csr_rw	1.670s	15.110us	1	1	100.00
		sram_ctrl_csr_aliasing	1.750s	45.652us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	30.741us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	33.130s	14.736ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.650s	26.397us	0	1	0.00
		sram_ctrl_tl_intg_err	2.840s	278.368us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.650s	26.397us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.840s	278.368us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.133m	10.021ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.133m	10.021ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.670s	15.110us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.547m	25.309ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.547m	25.309ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.547m	25.309ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	35.150s	10.510ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	7.950s	702.360us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	33.130s	14.736ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.300s	681.811us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	37.840s	3.580ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	37.840s	3.580ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.547m	25.309ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.650s	26.397us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	35.150s	10.510ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.650s	26.397us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.650s	26.397us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	37.840s	3.580ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.650s	26.397us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	23.120s	1.204ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.30098241010863768128097306792472981336075964055045445447845667516823096822284
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  26396754 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  26396754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---