SRAM_CTRL/RET Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.220s	302.130us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.730s	28.639us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.660s	23.055us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.670s	125.380us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.610s	21.725us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.990s	216.341us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.660s	23.055us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	21.725us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.340s	370.670us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.520s	271.700us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	25.890s	3.712ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.847m	6.543ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	36.740s	13.547ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.523m	11.761ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.690s	531.256us	1	1	100.00
V2	executable	sram_ctrl_executable	20.770s	463.028us	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.780s	767.742us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.093m	49.979ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	7.010s	237.473us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	19.050s	441.288us	1	1	100.00
		sram_ctrl_throughput_w_readback	2.850s	185.068us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.653m	20.754ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.670s	25.739us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	5.655m	15.219ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.920s	26.271us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.040s	446.758us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.040s	446.758us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.730s	28.639us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	23.055us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	21.725us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	25.361us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.730s	28.639us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	23.055us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	21.725us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	25.361us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.650s	1.651ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.820s	12.570us	0	1	0.00
		sram_ctrl_tl_intg_err	2.300s	341.718us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.820s	12.570us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.300s	341.718us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.653m	20.754ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.653m	20.754ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.660s	23.055us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	20.770s	463.028us	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	20.770s	463.028us	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	20.770s	463.028us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.690s	531.256us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.920s	504.639us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.650s	1.651ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.940s	29.239us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.220s	302.130us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.220s	302.130us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	20.770s	463.028us	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.820s	12.570us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.690s	531.256us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.820s	12.570us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.820s	12.570us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.220s	302.130us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.820s	12.570us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.247m	2.327ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.36496337542338972548568063107057372331512470695931001789108011026547541069331
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12570264 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12570264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---