SYSRST_CTRL Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.660s 2.134ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 6.870s 2.440ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.260s 2.398ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.820s 2.257ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 4.440s 6.083ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 3.790s 2.069ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 30.290s 59.215ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 4.170s 2.301ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 7.680s 2.049ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 3.790s 2.069ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.170s 2.301ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.501m 66.491ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 54.160s 27.582ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.410s 3.596ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 12.180s 5.887ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 8.880s 2.508ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.640s 2.087ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 4.520s 4.871ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 4.780s 2.623ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 8.070s 4.931ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 14.490s 30.571ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 13.060s 11.278ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.200s 2.062ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.460s 2.039ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 6.410s 2.109ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 6.410s 2.109ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 4.440s 6.083ms 1 1 100.00
sysrst_ctrl_csr_rw 3.790s 2.069ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.170s 2.301ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.360s 7.719ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 4.440s 6.083ms 1 1 100.00
sysrst_ctrl_csr_rw 3.790s 2.069ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.170s 2.301ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.360s 7.719ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 42.810s 22.012ms 1 1 100.00
sysrst_ctrl_tl_intg_err 1.471m 42.367ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.471m 42.367ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 9.880s 4.786ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00