UART Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: a29a8cc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.640s	428.631us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.480s	32.754us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.530s	34.620us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.030s	95.157us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.670s	32.715us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.570s	258.409us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.530s	34.620us	1	1	100.00
		uart_csr_aliasing	1.670s	32.715us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	11.820s	21.238ms	1	1	100.00
V2	parity	uart_smoke	2.640s	428.631us	1	1	100.00
		uart_tx_rx	11.820s	21.238ms	1	1	100.00
V2	parity_error	uart_intr	9.530s	19.134ms	1	1	100.00
		uart_rx_parity_err	10.240s	33.546ms	1	1	100.00
V2	watermark	uart_tx_rx	11.820s	21.238ms	1	1	100.00
		uart_intr	9.530s	19.134ms	1	1	100.00
V2	fifo_full	uart_fifo_full	13.700s	39.337ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	10.490s	82.016ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	3.674m	127.883ms	1	1	100.00
V2	rx_frame_err	uart_intr	9.530s	19.134ms	1	1	100.00
V2	rx_break_err	uart_intr	9.530s	19.134ms	1	1	100.00
V2	rx_timeout	uart_intr	9.530s	19.134ms	1	1	100.00
V2	perf	uart_perf	9.120m	15.193ms	1	1	100.00
V2	sys_loopback	uart_loopback	1.430s	18.424us	1	1	100.00
V2	line_loopback	uart_loopback	1.430s	18.424us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	29.750s	28.610ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.860s	4.598ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	5.550s	9.515ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	31.520s	5.380ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.938m	130.236ms	1	1	100.00
V2	stress_all	uart_stress_all	9.022m	59.989ms	1	1	100.00
V2	alert_test	uart_alert_test	1.490s	17.774us	1	1	100.00
V2	intr_test	uart_intr_test	1.530s	16.916us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.410s	38.336us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.410s	38.336us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.480s	32.754us	1	1	100.00
		uart_csr_rw	1.530s	34.620us	1	1	100.00
		uart_csr_aliasing	1.670s	32.715us	1	1	100.00
		uart_same_csr_outstanding	1.450s	35.478us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.480s	32.754us	1	1	100.00
		uart_csr_rw	1.530s	34.620us	1	1	100.00
		uart_csr_aliasing	1.670s	32.715us	1	1	100.00
		uart_same_csr_outstanding	1.450s	35.478us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.670s	230.492us	1	1	100.00
		uart_tl_intg_err	1.760s	106.866us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.760s	106.866us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.012m	23.036ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00