CHIP Simulation Results

Thursday May 01 2025 18:38:27 UTC

GitHub Revision: `a29a8cc`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.452m	3.191ms	1	1	100.00
		chip_sw_example_rom	1.048m	3.156ms	1	1	100.00
		chip_sw_example_manufacturer	2.203m	3.324ms	1	1	100.00
		chip_sw_example_concurrency	2.712m	2.823ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	4.084m	7.472ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.231m	3.533ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.086m	5.848ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	49.836m	26.464ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	4.337m	7.174ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	49.836m	26.464ms	1	1	100.00
		chip_csr_rw	3.231m	3.533ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.520s	207.388us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.921m	4.221ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.921m	4.221ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.921m	4.221ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.649m	4.857ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.649m	4.857ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.083m	4.268ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.723m	3.506ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.442m	4.831ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	17.213m	8.212ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.268m	4.345ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.507m	8.576ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.711m	4.773ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.711m	4.773ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.013m	4.037ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.312m	4.613ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.900m	3.904ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.632m	3.128ms	1	1	100.00
		chip_tap_straps_testunlock0	5.238m	5.561ms	1	1	100.00
		chip_tap_straps_rma	4.986m	5.019ms	1	1	100.00
		chip_tap_straps_prod	18.608m	19.073ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.014m	2.822ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.347m	10.010ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.657m	5.073ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.657m	5.073ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.469m	8.419ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	41.828m	25.594ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.193m	4.200ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.777m	6.095ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.429m	17.539ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.747m	3.072ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.473m	5.703ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.119m	2.511ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.797m	7.104ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.620m	2.570ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.445m	4.426ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.910m	2.741ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.315m	2.520ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.021m	4.894ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.880m	5.913ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.534m	2.533ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.880m	5.913ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.288m	2.718ms	1	1	100.00
		chip_sw_aes_smoketest	3.018m	2.714ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.584m	2.853ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.650m	3.079ms	1	1	100.00
		chip_sw_csrng_smoketest	2.483m	3.062ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.533m	3.917ms	1	1	100.00
		chip_sw_gpio_smoketest	2.787m	2.964ms	1	1	100.00
		chip_sw_hmac_smoketest	3.339m	3.002ms	1	1	100.00
		chip_sw_kmac_smoketest	3.421m	2.755ms	1	1	100.00
		chip_sw_otbn_smoketest	13.257m	8.640ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.763m	6.349ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	2.777m	4.673ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.526m	3.070ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.734m	2.865ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.475m	2.845ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.433m	2.842ms	1	1	100.00
		chip_sw_uart_smoketest	2.465m	2.468ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.796m	2.548ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.766m	5.054ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.965h	61.403ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.557m	15.070ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.688m	6.142ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.357m	3.405ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.594m	2.768ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.856h	54.899ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.853h	55.999ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.161m	2.507ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.161m	2.507ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	49.836m	26.464ms	1	1	100.00
		chip_same_csr_outstanding	40.140m	31.854ms	1	1	100.00
		chip_csr_hw_reset	4.084m	7.472ms	1	1	100.00
		chip_csr_rw	3.231m	3.533ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	49.836m	26.464ms	1	1	100.00
		chip_same_csr_outstanding	40.140m	31.854ms	1	1	100.00
		chip_csr_hw_reset	4.084m	7.472ms	1	1	100.00
		chip_csr_rw	3.231m	3.533ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	17.280s	343.244us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.810s	49.147us	1	1	100.00
		xbar_smoke_large_delays	58.120s	9.460ms	1	1	100.00
		xbar_smoke_slow_rsp	36.400s	4.017ms	1	1	100.00
		xbar_random_zero_delays	16.870s	314.038us	1	1	100.00
		xbar_random_large_delays	2.906m	29.869ms	1	1	100.00
		xbar_random_slow_rsp	2.744m	18.637ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	19.080s	741.478us	1	1	100.00
		xbar_error_and_unmapped_addr	23.020s	827.734us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	16.550s	274.010us	1	1	100.00
		xbar_error_and_unmapped_addr	23.020s	827.734us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	5.680s	71.475us	1	1	100.00
		xbar_access_same_device_slow_rsp	2.890m	20.707ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	21.220s	1.194ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.207m	3.651ms	1	1	100.00
		xbar_stress_all_with_error	32.650s	632.858us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.953m	473.774us	1	1	100.00
		xbar_stress_all_with_reset_error	5.131m	13.662ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.557m	15.070ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.338m	25.272ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.707m	15.003ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.430m	10.745ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.365m	15.728ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.082m	15.503ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.541m	16.106ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	37.760m	15.254ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.730s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	28.100s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	36.010s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.130s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	28.630s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	28.430s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	29.840s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	28.410s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.280s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.680s	10.400us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	27.300s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	27.700s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	27.390s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	27.320s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.660s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.850s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.700s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.910s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.900s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.830s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.440s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.480s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	27.740s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.450s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.830s	10.200us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.879m	11.166ms	1	1	100.00
		rom_e2e_asm_init_dev	37.068m	15.357ms	1	1	100.00
		rom_e2e_asm_init_prod	37.058m	15.131ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.890m	15.345ms	1	1	100.00
		rom_e2e_asm_init_rma	35.949m	14.762ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.385m	15.223ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.169m	15.109ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.806m	14.964ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.751m	16.433ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.290m	35.171ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.290m	35.171ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.557m	3.609ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.747m	3.072ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.318m	2.710ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.103m	3.170ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.915m	9.800ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.423m	2.390ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.308m	5.037ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.702m	4.269ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.985m	5.429ms	1	1	100.00
		chip_plic_all_irqs_10	4.376m	2.852ms	1	1	100.00
		chip_plic_all_irqs_20	5.948m	4.392ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.137m	2.738ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.365m	13.258ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.639m	4.458ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.063m	2.962ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.852m	9.892ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.536m	7.745ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.361m	7.023ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.415m	8.096ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.249h	255.213ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.401m	3.446ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.763m	6.349ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.401m	3.446ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.240m	8.618ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.240m	8.618ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.444m	7.069ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.741m	6.018ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.364m	6.068ms	1	1	100.00
		chip_sw_aes_idle	2.103m	3.170ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.680m	2.942ms	1	1	100.00
		chip_sw_kmac_idle	2.013m	2.170ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.612m	4.888ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.070m	3.359ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.519m	3.664ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.697m	4.625ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.225m	9.870ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.442m	3.696ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.027m	4.268ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.581m	4.049ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.004m	4.455ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.527m	3.989ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.562m	4.453ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.469m	8.419ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	7.802m	12.169ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.581m	4.049ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.004m	4.455ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.193m	4.200ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.777m	6.095ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.429m	17.539ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.747m	3.072ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.473m	5.703ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.119m	2.511ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.797m	7.104ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.620m	2.570ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.445m	4.426ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.910m	2.741ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.064m	2.534ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.764m	4.460ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.841m	7.662ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	47.549m	23.998ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.100m	2.400ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.424m	3.009ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	12.389m	8.811ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.704m	3.187ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.361m	4.416ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	16.448m	19.171ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	40.654m	23.370ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.469m	8.419ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.139m	4.957ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.194m	3.298ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.702m	4.269ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.536m	7.745ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.135m	6.550ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.802m	2.897ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.204m	6.746ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.907m	3.040ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	47.537m	17.653ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.026m	2.880ms	1	1	100.00
		chip_sw_edn_entropy_reqs	13.019m	7.048ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.026m	2.880ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.135m	6.550ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.243m	2.380ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	16.164m	15.775ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.999m	5.915ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.777m	6.095ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.951m	4.221ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.193m	4.200ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	50.918m	42.727ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	16.164m	15.775ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.567m	3.327ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	26.433m	13.605ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.469m	5.944ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	50.918m	42.727ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.469m	5.944ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.469m	5.944ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.469m	5.944ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.469m	5.944ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.702m	4.269ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.753m	6.374ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.695m	5.596ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.542m	5.027ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.542m	5.027ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.319m	2.609ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.119m	2.511ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.680m	2.942ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.162m	3.263ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	14.665m	7.548ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.566m	4.468ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.495m	4.809ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.213m	4.710ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.390m	3.410ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	26.433m	13.605ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.797m	7.104ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	28.336m	13.072ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.915m	9.800ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	36.799m	14.120ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.301m	2.975ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.711m	3.045ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.620m	2.570ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	26.433m	13.605ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	7.962m	11.930ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.944m	2.700ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	9.254m	5.589ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.013m	2.170ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.308m	5.037ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.632m	3.128ms	1	1	100.00
		chip_tap_straps_rma	4.986m	5.019ms	1	1	100.00
		chip_tap_straps_prod	18.608m	19.073ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.394m	3.356ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	7.962m	11.930ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	7.962m	11.930ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	7.962m	11.930ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	23.666m	12.065ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.469m	5.944ms	1	1	100.00
		chip_sw_flash_rma_unlocked	50.918m	42.727ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.453m	3.035ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.883m	7.694ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.780m	8.532ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.676m	5.734ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.962m	11.930ms	1	1	100.00
		chip_sw_keymgr_key_derivation	26.433m	13.605ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.904m	8.764ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.444m	9.540ms	1	1	100.00
		chip_prim_tl_access	1.753m	6.374ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	7.802m	12.169ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.442m	3.696ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.027m	4.268ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.581m	4.049ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.004m	4.455ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.527m	3.989ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.562m	4.453ms	1	1	100.00
		chip_tap_straps_dev	2.632m	3.128ms	1	1	100.00
		chip_tap_straps_rma	4.986m	5.019ms	1	1	100.00
		chip_tap_straps_prod	18.608m	19.073ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.247m	17.300ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.533m	4.242ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.845m	2.777ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.778m	3.157ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.361m	3.664ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	25.609m	36.377ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.247m	17.300ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	58.994m	47.515ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.018h	50.111ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	10.691m	11.422ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	57.855m	47.584ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	25.609m	36.377ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.413m	2.456ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.087m	2.723ms	1	1	100.00
		rom_volatile_raw_unlock	1.156m	2.579ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	52.487m	16.505ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.429m	17.539ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.364m	6.068ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.364m	6.068ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.364m	6.068ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	3.931m	3.579ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	7.962m	11.930ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	16.164m	15.775ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.931m	3.579ms	1	1	100.00
		chip_sw_keymgr_key_derivation	26.433m	13.605ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.807m	3.837ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.421m	3.064ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	16.164m	15.775ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.931m	3.579ms	1	1	100.00
		chip_sw_keymgr_key_derivation	26.433m	13.605ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.807m	3.837ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.421m	3.064ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	7.962m	11.930ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.582m	4.424ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.394m	3.356ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.453m	3.035ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.883m	7.694ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.780m	8.532ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.676m	5.734ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.962m	11.930ms	1	1	100.00
		chip_prim_tl_access	1.753m	6.374ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.753m	6.374ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.581m	8.201ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.820m	6.950ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.440m	28.604ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.317m	7.481ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.749m	7.747ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.689m	6.894ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	18.004m	22.157ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.869m	14.487ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.240m	8.618ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	14.998m	10.840ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.651m	4.340ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.820m	6.950ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.400m	4.472ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	33.069m	38.251ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.103m	7.940ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.817m	4.857ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.587m	26.614ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	2.202m	2.680ms	0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs	17.329m	12.909ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	16.888m	22.335ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.202m	3.245ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.702m	4.269ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.904m	8.764ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.904m	8.764ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	17.329m	12.909ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.587m	26.614ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.651m	4.340ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.763m	6.349ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.495m	4.269ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.775m	4.542ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.362m	4.653ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.365m	13.258ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.904m	2.326ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.702m	4.269ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	12.361m	7.023ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.576m	4.764ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.409m	4.716ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.591m	2.997ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.421m	3.064ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.775m	4.542ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.775m	4.542ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	9.143m	9.840ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.208m	13.468ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.495m	4.269ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.180m	3.750ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.195m	5.903ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.986m	5.019ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.247m	17.300ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.985m	5.429ms	1	1	100.00
		chip_plic_all_irqs_10	4.376m	2.852ms	1	1	100.00
		chip_plic_all_irqs_20	5.948m	4.392ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.964m	2.068ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.763m	3.282ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.557m	15.070ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.893m	7.071ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.737m	2.918ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.157m	3.936ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.173m	2.735ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.807m	3.837ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.445m	4.426ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.580m	7.206ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.222m	8.236ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.444m	9.540ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.702m	4.269ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.657m	5.073ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	2.202m	2.680ms	0	1	0.00
		chip_sw_sysrst_ctrl_reset	13.460m	24.295ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.845m	2.394ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.921m	3.347ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.574m	4.666ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	13.460m	24.295ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	13.460m	24.295ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	2.014m	2.513ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	2.014m	2.513ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.160m	5.677ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.290m	35.171ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.320m	2.712ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.892m	2.400ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.971m	3.994ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.889m	4.202ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.018m	8.070ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.287h	31.868ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	27.846m	11.773ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.173m	2.909ms	1	1	100.00
V2		TOTAL			237	275	86.18
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.846m	3.255ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.685m	2.455ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.444h	71.756ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.150m	3.688ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.510m	11.430ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.225m	12.086ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.077m	10.425ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.394m	4.032ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.364m	3.609ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.895m	3.836ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	22.756s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.802m	5.115ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.466m	2.390ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	15.800m	6.635ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	16.684m	7.691ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.247m	2.185ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.517m	5.673ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.059m	2.344ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.862m	4.053ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.152m	5.575ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.840m	3.885ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	17.329m	12.909ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.510m	11.430ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.225m	12.086ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.077m	10.425ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.667m	5.100ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.702m	4.269ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.409h	38.369ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.409h	38.369ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.474m	3.470ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.649m	4.857ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	48.071m	18.564ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.392m	2.269ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.646m	4.835ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.077m	3.010ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.495m	3.223ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.715m	3.471ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.467s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.021m	2.743ms	1	1	100.00
		TOTAL			284	325	87.38

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.66102575358050795438786558549190821774690358273286752766876066300468382115266
    Line 679, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.12021255597403015175314791311091076948139705051420851983024870773539093753986
    Line 660, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.58320438422006057581427444466637497657931450261974214970578760183370070985623
    Line 653, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.65397183009466234688157438143391931061700594342696129368892041467209765660862
    Line 781, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.87086240884235471723229176547822888457637899197513304538506340504367236692886
    Line 614, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.109783572501441154905481176785657707944613111799888124327019917122511134815084
    Line 740, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.80158101940312290315531300203087640448250955263479872476716441548994282817049
    Line 685, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.86368283299528188275055488002996667229709890087526615510635270325030925664118
    Line 689, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.54791912591514165022385998792661759155563509874768210352568298890601198685569
    Line 662, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1350340389909651472680913797732394881838527220493837621575823735757736713114
    Line 689, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.27359786235341344412133325736672146834185474135617884011070120627702041040031
    Line 768, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.86863543718763723900940166158365486652687440925736038471549435177659720543399
    Line 708, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.72379037866623271501288818130661940514309330263754187840138587445176819750802
    Line 664, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.13042340372550404765346851608951732634725982964509019821763255920849777723197
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.144s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.97172894896251252717126375573056765597186469394493633595823390260149071810321
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 13.133s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.70610207444631944173272628039580253379363957970138869728215865609548724670243
    Line 755, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.4617894086820106535137842399202312866318926641440544953315485172118031596793
    Line 745, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.41535256640765020490832730632419618152774200872441606750368288966077915080374
    Line 795, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.47135520665659007915371734199186352272971021600521260914577410877159255844660
    Line 711, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.74490832749648183835606487454267425861149621755118318078436929504129138779544
    Line 619, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 4036.521500 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 4036.521500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.54570063897313204533525578072663848191155817294246470530141409328525847127358
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2918.412912 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2918.412912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@100381) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.84822606291630091137788765419253132331612226066491005314905083352800705479147
Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4542.128672 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@100381) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4542.128672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:43)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns * has 1 failures:
- Test chip_sw_pwrmgr_sysrst_ctrl_reset has 1 failures.
  - 0.chip_sw_pwrmgr_sysrst_ctrl_reset.88609689970747768839408391798820152940643182344571634802986478638749528691854
    Line 413, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest/run.log
```
  UVM_ERROR @ 2679.850884 us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:43)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns 3
  UVM_INFO @ 2679.850884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:134)] DIF-fail: dif_pwrmgr_set_request_sources(&pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns * has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.42112674510794403196760156046420802839890385140039602694496840437876599340210
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 2512.712790 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:134)] DIF-fail: dif_pwrmgr_set_request_sources(&pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns 3
  UVM_INFO @ 2512.712790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.92215933829256247335099699936210344840977612912383937792386601281780011445843
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35170.790014 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35170.790014 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.99902382608228217932093044201975936598183079980008032207391862107600779514096
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2389.699234 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2389.699234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.97675659234165604533894298882959135959751232292166187503553788760923873721855
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2961.563556 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2961.563556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.31467531984400620533866219227068036964705585010044141150458022695931080861046
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2896.895306 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2896.895306 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38183) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.115324561240427853598974608639283128150363575145596197186947575921702713642198
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2507.264680 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38183) { a_addr: 'h10400  a_data: 'h5794fea6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h195a4  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2507.264680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.71596737325540463841079125970684608228550803084082367575114400673438686007294
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3405.052000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3405.052000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.67075191320553143640211775669362644891033505470590142955805604797073892404148
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2768.318000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2768.318000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.8772439504056338603731078829789374194845908665500217215779334106994749171834
    Line 435, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 25593.956615 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 25593.956615 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.21290373991895498929218491432427881641383913490482514539035753557960201447452
    Line 461, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3687.931494 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3687.931494 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.110415811777360954579967825903269606309826316884594185668364117180190134243327
    Line 716, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.53208988817995780186407146594638920891664256585639457238643628308632419246138
    Line 659, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```