ADC_CTRL Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.930s	5.675ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.260s	1.299ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.220s	340.753us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	18.280s	26.877ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.970s	859.677us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.670s	551.173us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.220s	340.753us	1	1	100.00
		adc_ctrl_csr_aliasing	3.970s	859.677us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.306m	328.081ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.096m	328.405ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	14.973m	500.103ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	3.558m	485.155ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	4.059m	554.179ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	10.523m	402.731ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.297m	184.685ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.270m	83.594ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	10.820s	5.200ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	59.490s	36.252ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	40.400s	68.646ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	1.143m	166.583ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.150s	470.283us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.200s	490.312us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.390s	506.459us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.390s	506.459us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.260s	1.299ms	1	1	100.00
		adc_ctrl_csr_rw	2.220s	340.753us	1	1	100.00
		adc_ctrl_csr_aliasing	3.970s	859.677us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.020s	4.495ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.260s	1.299ms	1	1	100.00
		adc_ctrl_csr_rw	2.220s	340.753us	1	1	100.00
		adc_ctrl_csr_aliasing	3.970s	859.677us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.020s	4.495ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	14.810s	8.131ms	1	1	100.00
		adc_ctrl_tl_intg_err	16.600s	7.889ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	16.600s	7.889ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.630s	4.888ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.74010936118560388551420886456789712549308186805568828336404886262976527559364
      Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 83593995870 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 83593995870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---