EDN Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.680s	37.811us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.840s	20.610us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.720s	21.943us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.320s	269.910us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.790s	16.973us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.600s	36.265us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.720s	21.943us	1	1	100.00
		edn_csr_aliasing	1.790s	16.973us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.820s	52.698us	1	1	100.00
V2	csrng_commands	edn_genbits	2.820s	52.698us	1	1	100.00
V2	genbits	edn_genbits	2.820s	52.698us	1	1	100.00
V2	interrupts	edn_intr	1.850s	35.227us	1	1	100.00
V2	alerts	edn_alert	2.310s	66.422us	1	1	100.00
V2	errs	edn_err	2.060s	19.270us	1	1	100.00
V2	disable	edn_disable	1.730s	33.461us	1	1	100.00
		edn_disable_auto_req_mode	2.000s	36.092us	1	1	100.00
V2	stress_all	edn_stress_all	3.620s	312.511us	1	1	100.00
V2	intr_test	edn_intr_test	1.780s	24.110us	1	1	100.00
V2	alert_test	edn_alert_test	1.770s	13.620us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.230s	88.823us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.230s	88.823us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.840s	20.610us	1	1	100.00
		edn_csr_rw	1.720s	21.943us	1	1	100.00
		edn_csr_aliasing	1.790s	16.973us	1	1	100.00
		edn_same_csr_outstanding	1.890s	50.041us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.840s	20.610us	1	1	100.00
		edn_csr_rw	1.720s	21.943us	1	1	100.00
		edn_csr_aliasing	1.790s	16.973us	1	1	100.00
		edn_same_csr_outstanding	1.890s	50.041us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	7.740s	9.767ms	1	1	100.00
		edn_tl_intg_err	2.290s	98.914us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.690s	17.305us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.310s	66.422us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.740s	9.767ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.740s	9.767ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.740s	9.767ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.740s	9.767ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.310s	66.422us	1	1	100.00
		edn_sec_cm	7.740s	9.767ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.310s	66.422us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.290s	98.914us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.185m	8.601ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00