1a62881| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | entropy_src_smoke | 4.000s | 26.895us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | entropy_src_csr_hw_reset | 5.000s | 276.433us | 1 | 1 | 100.00 |
| V1 | csr_rw | entropy_src_csr_rw | 5.000s | 27.712us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | entropy_src_csr_bit_bash | 6.000s | 174.626us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | entropy_src_csr_aliasing | 6.000s | 44.786us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 4.000s | 36.981us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 5.000s | 27.712us | 1 | 1 | 100.00 |
| entropy_src_csr_aliasing | 6.000s | 44.786us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | firmware | entropy_src_smoke | 4.000s | 26.895us | 1 | 1 | 100.00 |
| entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 | ||
| entropy_src_fw_ov | 2.217m | 7.041ms | 1 | 1 | 100.00 | ||
| V2 | firmware_mode | entropy_src_fw_ov | 2.217m | 7.041ms | 1 | 1 | 100.00 |
| V2 | rng_mode | entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 |
| V2 | rng_max_rate | entropy_src_rng_max_rate | 4.000s | 71.444us | 0 | 1 | 0.00 |
| V2 | health_checks | entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 |
| V2 | conditioning | entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 |
| V2 | interrupts | entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 |
| entropy_src_intr | 8.000s | 1.239ms | 1 | 1 | 100.00 | ||
| V2 | alerts | entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 |
| entropy_src_functional_alerts | 5.000s | 231.251us | 1 | 1 | 100.00 | ||
| V2 | stress_all | entropy_src_stress_all | 1.717m | 11.356ms | 1 | 1 | 100.00 |
| V2 | functional_errors | entropy_src_functional_errors | 5.000s | 85.254us | 1 | 1 | 100.00 |
| V2 | firmware_ov_read_contiguous_data | entropy_src_fw_ov_contiguous | 10.000s | 238.870us | 1 | 1 | 100.00 |
| V2 | intr_test | entropy_src_intr_test | 4.000s | 45.528us | 1 | 1 | 100.00 |
| V2 | alert_test | entropy_src_alert_test | 4.000s | 106.554us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 7.000s | 61.647us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | entropy_src_tl_errors | 7.000s | 61.647us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 5.000s | 276.433us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 5.000s | 27.712us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 6.000s | 44.786us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 6.000s | 138.297us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 5.000s | 276.433us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 5.000s | 27.712us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 6.000s | 44.786us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 6.000s | 138.297us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 10 | 12 | 83.33 | |||
| V2S | tl_intg_err | entropy_src_sec_cm | 5.000s | 68.800us | 1 | 1 | 100.00 |
| entropy_src_tl_intg_err | 6.000s | 366.252us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_regwen | entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 |
| entropy_src_cfg_regwen | 5.000s | 22.265us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_mubi | entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 |
| V2S | sec_cm_config_redun | entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 |
| V2S | sec_cm_intersig_mubi | entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 |
| entropy_src_fw_ov | 2.217m | 7.041ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 85.254us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 68.800us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 85.254us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 68.800us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 5.000s | 7.765us | 0 | 1 | 0.00 |
| V2S | sec_cm_fifo_ctr_redun | entropy_src_functional_errors | 5.000s | 85.254us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 68.800us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 5.000s | 85.254us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 68.800us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 5.000s | 85.254us | 1 | 1 | 100.00 |
| V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 5.000s | 231.251us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 6.000s | 366.252us | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 14.000s | 2.311ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 19 | 22 | 86.36 |
UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts has 2 failures:
Test entropy_src_rng has 1 failures.
0.entropy_src_rng.81476903095321924738747410531722410441086371617638318098511491528000109836671
Line 155, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng/latest/run.log
UVM_ERROR @ 7765003 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2 [0x2]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 7765003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test entropy_src_rng_with_xht_rsps has 1 failures.
0.entropy_src_rng_with_xht_rsps.15517896747960077173757360991186435871342077820053876230391539633134029432240
Line 471, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_with_xht_rsps/latest/run.log
UVM_ERROR @ 2310680383 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 2310680383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_*/entropy_src_csr_assert_fpv.sv,294): Assertion conf_rd_A has failed has 1 failures:
0.entropy_src_rng_max_rate.72592770051309478159649336775035150445145656649860307226824844849477426317005
Line 203, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_max_rate/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,294): (time 71443551 PS) Assertion tb.dut.entropy_src_csr_assert.conf_rd_A has failed
UVM_ERROR @ 71443551 ps: (entropy_src_csr_assert_fpv.sv:294) [ASSERT FAILED] conf_rd_A
UVM_INFO @ 71443551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---