HMAC Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.610s 206.808us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.920s 26.984us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.850s 50.556us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.650s 111.731us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.320s 599.948us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 3.566m 87.337ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.850s 50.556us 1 1 100.00
hmac_csr_aliasing 7.320s 599.948us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 15.650s 4.828ms 1 1 100.00
V2 back_pressure hmac_back_pressure 30.720s 874.486us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.801m 35.741ms 1 1 100.00
hmac_test_sha384_vectors 6.457m 24.702ms 1 1 100.00
hmac_test_sha512_vectors 20.380s 252.559us 1 1 100.00
hmac_test_hmac256_vectors 10.360s 1.262ms 1 1 100.00
hmac_test_hmac384_vectors 12.490s 956.239us 1 1 100.00
hmac_test_hmac512_vectors 11.590s 809.285us 1 1 100.00
V2 burst_wr hmac_burst_wr 21.190s 3.176ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.774m 9.490ms 1 1 100.00
V2 error hmac_error 36.310s 2.859ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.213m 4.209ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.610s 206.808us 1 1 100.00
hmac_long_msg 15.650s 4.828ms 1 1 100.00
hmac_back_pressure 30.720s 874.486us 1 1 100.00
hmac_datapath_stress 4.774m 9.490ms 1 1 100.00
hmac_burst_wr 21.190s 3.176ms 1 1 100.00
hmac_stress_all 9.852m 5.215ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.610s 206.808us 1 1 100.00
hmac_long_msg 15.650s 4.828ms 1 1 100.00
hmac_back_pressure 30.720s 874.486us 1 1 100.00
hmac_datapath_stress 4.774m 9.490ms 1 1 100.00
hmac_wipe_secret 1.213m 4.209ms 1 1 100.00
hmac_test_sha256_vectors 2.801m 35.741ms 1 1 100.00
hmac_test_sha384_vectors 6.457m 24.702ms 1 1 100.00
hmac_test_sha512_vectors 20.380s 252.559us 1 1 100.00
hmac_test_hmac256_vectors 10.360s 1.262ms 1 1 100.00
hmac_test_hmac384_vectors 12.490s 956.239us 1 1 100.00
hmac_test_hmac512_vectors 11.590s 809.285us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.610s 206.808us 1 1 100.00
hmac_long_msg 15.650s 4.828ms 1 1 100.00
hmac_back_pressure 30.720s 874.486us 1 1 100.00
hmac_datapath_stress 4.774m 9.490ms 1 1 100.00
hmac_burst_wr 21.190s 3.176ms 1 1 100.00
hmac_error 36.310s 2.859ms 1 1 100.00
hmac_wipe_secret 1.213m 4.209ms 1 1 100.00
hmac_test_sha256_vectors 2.801m 35.741ms 1 1 100.00
hmac_test_sha384_vectors 6.457m 24.702ms 1 1 100.00
hmac_test_sha512_vectors 20.380s 252.559us 1 1 100.00
hmac_test_hmac256_vectors 10.360s 1.262ms 1 1 100.00
hmac_test_hmac384_vectors 12.490s 956.239us 1 1 100.00
hmac_test_hmac512_vectors 11.590s 809.285us 1 1 100.00
hmac_stress_all 9.852m 5.215ms 1 1 100.00
V2 stress_all hmac_stress_all 9.852m 5.215ms 1 1 100.00
V2 alert_test hmac_alert_test 1.510s 20.639us 1 1 100.00
V2 intr_test hmac_intr_test 2.030s 15.293us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.900s 108.383us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.900s 108.383us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.920s 26.984us 1 1 100.00
hmac_csr_rw 1.850s 50.556us 1 1 100.00
hmac_csr_aliasing 7.320s 599.948us 1 1 100.00
hmac_same_csr_outstanding 2.290s 126.427us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.920s 26.984us 1 1 100.00
hmac_csr_rw 1.850s 50.556us 1 1 100.00
hmac_csr_aliasing 7.320s 599.948us 1 1 100.00
hmac_same_csr_outstanding 2.290s 126.427us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.860s 266.794us 1 1 100.00
hmac_tl_intg_err 3.070s 738.855us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.070s 738.855us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.610s 206.808us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.730s 138.394us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.119m 16.277ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.490s 92.974us 1 1 100.00
TOTAL 28 28 100.00