I2C Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	15.380s	1.553ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	16.370s	9.918ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.740s	59.740us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.700s	19.138us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.020s	186.064us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.430s	453.319us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.780s	25.543us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.700s	19.138us	1	1	100.00
		i2c_csr_aliasing	2.430s	453.319us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.090s	204.314us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	17.358m	31.424ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	46.920s	10.619ms	1	1	100.00
V2	host_override	i2c_host_override	1.670s	82.894us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.320m	50.376ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	44.400s	9.787ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.860s	222.401us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.050s	301.193us	1	1	100.00
		i2c_host_fifo_reset_rx	7.980s	192.022us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.222m	3.439ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	30.030s	1.183ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.510s	28.518us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.240s	2.088ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	2.445m	21.258ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.810s	538.973us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	11.460s	1.338ms	1	1	100.00
		i2c_target_intr_smoke	6.500s	4.218ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.030s	398.192us	1	1	100.00
		i2c_target_fifo_reset_tx	2.520s	1.119ms	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.005m	56.371ms	1	1	100.00
		i2c_target_stress_rd	11.460s	1.338ms	1	1	100.00
		i2c_target_intr_stress_wr	50.150s	23.316ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.110s	5.185ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	17.840s	1.207ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.900s	2.773ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.400s	270.657us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.900s	439.134us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.240s	400.793us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	46.920s	10.619ms	1	1	100.00
		i2c_host_perf_precise	27.010s	2.921ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	30.030s	1.183ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	8.040s	512.022us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.150s	729.596us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.730s	991.771us	1	1	100.00
		i2c_target_nack_txstretch	2.200s	449.576us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.530s	402.257us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.610s	4.168ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.580s	18.042us	1	1	100.00
V2	intr_test	i2c_intr_test	1.620s	129.514us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.920s	127.447us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.920s	127.447us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.740s	59.740us	1	1	100.00
		i2c_csr_rw	1.700s	19.138us	1	1	100.00
		i2c_csr_aliasing	2.430s	453.319us	1	1	100.00
		i2c_same_csr_outstanding	1.820s	238.814us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.740s	59.740us	1	1	100.00
		i2c_csr_rw	1.700s	19.138us	1	1	100.00
		i2c_csr_aliasing	2.430s	453.319us	1	1	100.00
		i2c_same_csr_outstanding	1.820s	238.814us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.160s	168.942us	1	1	100.00
		i2c_sec_cm	1.840s	67.502us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.160s	168.942us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	13.600s	2.458ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.280s	5.177ms	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	27.310s	27.780ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.75129531330073026702055028592964644098308952946285396942833814529471069410616
      Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2457681778 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2457681778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.58199762347746225604465288089714519639481355922000133501999383901659393224941
      Line 161, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27779915057 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 27779915057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.94287738143553798915130050426964005477584834531038887238342937116169511198929
      Line 114, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 31424011565 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @16676142
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.91675823907685907955747880700817019693754033154246176822797365678210246612110
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 5177098261 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 240 [0xf0])
        UVM_INFO @ 5177098261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.61702747964993980052661193727407253198970845755641660327159453139214122000426
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @  28517737 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x6d633794, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @  28517737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.41725641399739768187697639411697068222203566863690219129787166356812014765536
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 449576412 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 449576412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---