KEYMGR Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.380s	1.146ms	1	1	100.00
V1	random	keymgr_random	4.370s	98.763us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.120s	118.526us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.960s	49.777us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.680s	4.106ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.830s	186.603us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.650s	13.073us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.960s	49.777us	0	1	0.00
		keymgr_csr_aliasing	3.830s	186.603us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	5.140s	407.085us	1	1	100.00
V2	sideload	keymgr_sideload	3.200s	139.465us	1	1	100.00
		keymgr_sideload_kmac	4.570s	150.720us	1	1	100.00
		keymgr_sideload_aes	3.650s	123.999us	1	1	100.00
		keymgr_sideload_otbn	3.240s	179.743us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.520s	217.575us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.890s	152.996us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.950s	609.049us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.450s	505.245us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.870s	96.669us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	5.970s	444.896us	1	1	100.00
V2	stress_all	keymgr_stress_all	1.057m	10.992ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.800s	7.181us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.700s	23.427us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.700s	259.363us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.700s	259.363us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.120s	118.526us	1	1	100.00
		keymgr_csr_rw	1.960s	49.777us	0	1	0.00
		keymgr_csr_aliasing	3.830s	186.603us	1	1	100.00
		keymgr_same_csr_outstanding	2.180s	28.372us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.120s	118.526us	1	1	100.00
		keymgr_csr_rw	1.960s	49.777us	0	1	0.00
		keymgr_csr_aliasing	3.830s	186.603us	1	1	100.00
		keymgr_same_csr_outstanding	2.180s	28.372us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
		keymgr_tl_intg_err	4.770s	352.726us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.750s	404.454us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.750s	404.454us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.750s	404.454us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.750s	404.454us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.810s	6.981us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.770s	352.726us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.750s	404.454us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	5.140s	407.085us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.370s	98.763us	1	1	100.00
		keymgr_csr_rw	1.960s	49.777us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.370s	98.763us	1	1	100.00
		keymgr_csr_rw	1.960s	49.777us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.370s	98.763us	1	1	100.00
		keymgr_csr_rw	1.960s	49.777us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.890s	152.996us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.870s	96.669us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.870s	96.669us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.370s	98.763us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	6.210s	741.167us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.240s	81.830us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.890s	152.996us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.240s	81.830us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.240s	81.830us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.240s	81.830us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.360s	1.872ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.240s	81.830us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	5.730s	173.608us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.64267621237979162770472025400141214056992200879054885408442443220792141050206
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @   6981009 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @   6981009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.48093452677845028683202846930771233136360875517795310324834567336211885707728
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
        UVM_ERROR @  49776868 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
        UVM_INFO @  49776868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.50762378412909444840961978946136578341437836815135156182301732953500132099314
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
        UVM_ERROR @  13072638 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
        UVM_INFO @  13072638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---