KMAC/MASKED Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	29.490s	1.992ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.860s	43.253us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.800s	38.725us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.280s	497.668us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.780s	385.111us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.770s	73.948us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.800s	38.725us	1	1	100.00
		kmac_csr_aliasing	6.780s	385.111us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.580s	13.156us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.070s	82.598us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	19.561m	72.958ms	1	1	100.00
V2	burst_write	kmac_burst_write	12.520m	30.675ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.490m	200.796ms	1	1	100.00
		kmac_test_vectors_sha3_256	31.040s	2.053ms	1	1	100.00
		kmac_test_vectors_sha3_384	27.900s	6.894ms	1	1	100.00
		kmac_test_vectors_sha3_512	2.440s	75.776us	0	1	0.00
		kmac_test_vectors_shake_128	27.272m	21.583ms	1	1	100.00
		kmac_test_vectors_shake_256	5.152m	38.453ms	1	1	100.00
		kmac_test_vectors_kmac	3.520s	407.416us	1	1	100.00
		kmac_test_vectors_kmac_xof	4.500s	199.551us	1	1	100.00
V2	sideload	kmac_sideload	5.861m	80.106ms	1	1	100.00
V2	app	kmac_app	2.747m	29.752ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.201m	43.806ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.894m	8.889ms	1	1	100.00
V2	error	kmac_error	1.638m	4.156ms	1	1	100.00
V2	key_error	kmac_key_error	5.210s	3.701ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.710s	1.347ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.790s	47.015us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.970s	84.565us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	51.010s	6.260ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.510s	93.697us	1	1	100.00
V2	stress_all	kmac_stress_all	12.820m	30.725ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.570s	158.237us	1	1	100.00
V2	alert_test	kmac_alert_test	1.760s	48.663us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.700s	147.641us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.700s	147.641us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.860s	43.253us	1	1	100.00
		kmac_csr_rw	1.800s	38.725us	1	1	100.00
		kmac_csr_aliasing	6.780s	385.111us	1	1	100.00
		kmac_same_csr_outstanding	2.900s	402.251us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.860s	43.253us	1	1	100.00
		kmac_csr_rw	1.800s	38.725us	1	1	100.00
		kmac_csr_aliasing	6.780s	385.111us	1	1	100.00
		kmac_same_csr_outstanding	2.900s	402.251us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.370s	304.617us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.370s	304.617us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.370s	304.617us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.370s	304.617us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.870s	411.462us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	52.100s	4.918ms	1	1	100.00
		kmac_tl_intg_err	2.620s	401.580us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.620s	401.580us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.510s	93.697us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	29.490s	1.992ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.861m	80.106ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.370s	304.617us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	52.100s	4.918ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	52.100s	4.918ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	52.100s	4.918ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	29.490s	1.992ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.510s	93.697us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	52.100s	4.918ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	23.190s	571.678us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	29.490s	1.992ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.513m	10.080ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_test_vectors_sha3_512 has 1 failures.

    • 0.kmac_test_vectors_sha3_512.87110593937091040604626577176788435630150400934928900395990844590313648896867
      Line 73, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest/run.log

        UVM_ERROR @  75775778 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  75775778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.84384662021116559247215430509727288685989308895463276339549760551000354421939
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @ 411462208 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @ 411462208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---