KMAC/UNMASKED Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	38.120s	9.333ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.990s	112.922us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.810s	34.651us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.530s	953.702us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.750s	393.604us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.400s	117.406us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.810s	34.651us	1	1	100.00
		kmac_csr_aliasing	7.750s	393.604us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.590s	30.938us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.920s	307.234us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	16.024m	168.844ms	1	1	100.00
V2	burst_write	kmac_burst_write	4.322m	8.635ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.834m	61.671ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.440s	2.149ms	1	1	100.00
		kmac_test_vectors_sha3_384	15.600s	422.692us	1	1	100.00
		kmac_test_vectors_sha3_512	11.645m	32.206ms	1	1	100.00
		kmac_test_vectors_shake_128	2.317m	9.792ms	1	1	100.00
		kmac_test_vectors_shake_256	1.547m	14.216ms	1	1	100.00
		kmac_test_vectors_kmac	3.170s	120.653us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.980s	109.389us	1	1	100.00
V2	sideload	kmac_sideload	6.012m	129.255ms	1	1	100.00
V2	app	kmac_app	3.729m	34.761ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	59.180s	4.019ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	50.200s	3.863ms	1	1	100.00
V2	error	kmac_error	2.717m	21.711ms	1	1	100.00
V2	key_error	kmac_key_error	4.260s	925.360us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	29.310s	10.135ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	18.630s	3.352ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	24.460s	7.054ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	23.900s	7.477ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	20.500s	4.031ms	1	1	100.00
V2	stress_all	kmac_stress_all	2.906m	13.697ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.730s	65.134us	1	1	100.00
V2	alert_test	kmac_alert_test	1.760s	35.260us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.660s	185.291us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.660s	185.291us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.990s	112.922us	1	1	100.00
		kmac_csr_rw	1.810s	34.651us	1	1	100.00
		kmac_csr_aliasing	7.750s	393.604us	1	1	100.00
		kmac_same_csr_outstanding	2.280s	44.457us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.990s	112.922us	1	1	100.00
		kmac_csr_rw	1.810s	34.651us	1	1	100.00
		kmac_csr_aliasing	7.750s	393.604us	1	1	100.00
		kmac_same_csr_outstanding	2.280s	44.457us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.900s	843.589us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.900s	843.589us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.900s	843.589us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.900s	843.589us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.800s	18.491us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	31.750s	31.859ms	1	1	100.00
		kmac_tl_intg_err	3.180s	215.124us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.180s	215.124us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	20.500s	4.031ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	38.120s	9.333ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.012m	129.255ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.900s	843.589us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	31.750s	31.859ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	31.750s	31.859ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	31.750s	31.859ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	38.120s	9.333ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	20.500s	4.031ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	31.750s	31.859ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.401m	88.096ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	38.120s	9.333ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.377m	5.787ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.62345533085713225290617619404207223691282682978989116592595289037919509076979
      Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10135361630 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc96d1000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
        UVM_INFO @ 10135361630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.25687477489606926360881639752922752861968915073845008553867591558239462026304
      Line 270, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5786966465 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 5786966465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.66033710385411205529210278195288574128651742712486208198091897598553364122248
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
        UVM_ERROR @  18490953 ps: (kmac_csr_assert_fpv.sv:517) [ASSERT FAILED] prefix_5_rd_A
        UVM_INFO @  18490953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---