OTBN Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	165.438us	1	1	100.00
V1	single_binary	otbn_single	10.000s	18.373us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	15.790us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	12.927us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	65.477us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	28.514us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	40.791us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	12.927us	1	1	100.00
		otbn_csr_aliasing	6.000s	28.514us	1	1	100.00
V1	mem_walk	otbn_mem_walk	28.000s	11.932ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	10.000s	222.812us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	30.000s	150.989us	1	1	100.00
V2	multi_error	otbn_multi_err	39.000s	692.606us	1	1	100.00
V2	back_to_back	otbn_multi	40.000s	868.838us	1	1	100.00
V2	stress_all	otbn_stress_all	11.000s	51.141us	1	1	100.00
V2	lc_escalation	otbn_escalate	10.000s	90.736us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	64.123us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	10.000s	55.145us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	14.536us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	12.586us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	8.000s	396.507us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	8.000s	396.507us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	15.790us	1	1	100.00
		otbn_csr_rw	6.000s	12.927us	1	1	100.00
		otbn_csr_aliasing	6.000s	28.514us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	45.098us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	15.790us	1	1	100.00
		otbn_csr_rw	6.000s	12.927us	1	1	100.00
		otbn_csr_aliasing	6.000s	28.514us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	45.098us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	17.637us	1	1	100.00
		otbn_dmem_err	8.000s	37.275us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	250.134us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	199.188us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	181.871us	1	1	100.00
		otbn_urnd_err	11.000s	28.119us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	43.232us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	69.333us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	72.131us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	11.000s	287.052us	0	1	0.00
		otbn_tl_intg_err	12.000s	368.112us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	20.000s	694.162us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	165.438us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	8.000s	37.275us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	17.637us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	12.000s	368.112us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	10.000s	90.736us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	17.637us	1	1	100.00
		otbn_dmem_err	8.000s	37.275us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	64.123us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	43.232us	1	1	100.00
		otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	10.000s	18.373us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	17.637us	1	1	100.00
		otbn_dmem_err	8.000s	37.275us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	64.123us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	43.232us	1	1	100.00
		otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	10.000s	90.736us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	17.637us	1	1	100.00
		otbn_dmem_err	8.000s	37.275us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	64.123us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	43.232us	1	1	100.00
		otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	10.000s	18.373us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	16.000s	60.113us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	22.766us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	32.000s	590.193us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	32.000s	590.193us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	55.883us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	61.225us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	34.450us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	34.450us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	1.483m	482.174us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	10.000s	18.373us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	10.000s	18.373us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	10.000s	18.373us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	40.000s	868.838us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	10.000s	18.373us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	10.000s	18.373us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	17.469us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	10.000s	18.373us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	11.000s	287.052us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	31.000s	361.296us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.7809810753121905577044567304525638309970949644915798203096896221015159594010
      Line 185, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 361296142 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 361296142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.100794601775770380159827540639202864907641455193523142842229926929215315809265
      Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 482173584 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @ 482173584 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @ 482173584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.94859186456289669642936098145837343221576891047747448072732588261803999351035
      Line 116, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 287051950 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 287051950 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @ 287051950 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @ 287051950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---