RV_TIMER Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.520s	39.220us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.590s	15.419us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.580s	26.798us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.800s	209.254us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.490s	71.574us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.660s	246.037us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.580s	26.798us	1	1	100.00
		rv_timer_csr_aliasing	1.490s	71.574us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.760s	699.383us	1	1	100.00
V2	disabled	rv_timer_disabled	3.380s	1.550ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	6.624m	342.927ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	6.624m	342.927ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.670s	141.641us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.480s	40.835us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.620s	46.681us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.300s	274.463us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.300s	274.463us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.590s	15.419us	1	1	100.00
		rv_timer_csr_rw	1.580s	26.798us	1	1	100.00
		rv_timer_csr_aliasing	1.490s	71.574us	1	1	100.00
		rv_timer_same_csr_outstanding	1.560s	34.320us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.590s	15.419us	1	1	100.00
		rv_timer_csr_rw	1.580s	26.798us	1	1	100.00
		rv_timer_csr_aliasing	1.490s	71.574us	1	1	100.00
		rv_timer_same_csr_outstanding	1.560s	34.320us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.740s	655.181us	1	1	100.00
		rv_timer_tl_intg_err	1.940s	88.297us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.940s	88.297us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	19.800s	13.226ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.560s	17.908us	1	1	100.00
		rv_timer_max	1.480s	33.633us	1	1	100.00
		TOTAL			19	19	100.00