SPI_DEVICE/1R1W Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.426m	52.642ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.980s	20.501us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.420s	338.092us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.400s	372.602us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.140s	2.412ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.400s	217.403us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.420s	338.092us	1	1	100.00
		spi_device_csr_aliasing	6.140s	2.412ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.520s	17.196us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.170s	54.954us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.790s	123.375us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.500s	1.381us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.530s	9.569us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.870s	32.102us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.870s	32.102us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.320s	2.183ms	1	1	100.00
		spi_device_tpm_sts_read	2.000s	145.222us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	16.300s	1.776ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	13.340s	15.965ms	1	1	100.00
		spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.300s	10.027ms	1	1	100.00
		spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.300s	10.027ms	1	1	100.00
		spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.510s	201.891us	1	1	100.00
		spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.510s	201.891us	1	1	100.00
		spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.510s	201.891us	1	1	100.00
		spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.510s	201.891us	1	1	100.00
		spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.510s	201.891us	1	1	100.00
		spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.170s	217.402us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	15.890s	13.940ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	15.890s	13.940ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	15.890s	13.940ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	8.460s	815.353us	1	1	100.00
		spi_device_read_buffer_direct	3.490s	529.445us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	15.890s	13.940ms	1	1	100.00
		spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	43.490s	7.030ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.790s	31.617us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.790s	31.617us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.426m	52.642ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	30.500s	15.843ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.000s	476.646us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.870s	43.014us	1	1	100.00
V2	intr_test	spi_device_intr_test	2.210s	34.092us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.420s	131.836us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.420s	131.836us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.980s	20.501us	1	1	100.00
		spi_device_csr_rw	2.420s	338.092us	1	1	100.00
		spi_device_csr_aliasing	6.140s	2.412ms	1	1	100.00
		spi_device_same_csr_outstanding	3.550s	206.877us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.980s	20.501us	1	1	100.00
		spi_device_csr_rw	2.420s	338.092us	1	1	100.00
		spi_device_csr_aliasing	6.140s	2.412ms	1	1	100.00
		spi_device_same_csr_outstanding	3.550s	206.877us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.550s	361.034us	1	1	100.00
		spi_device_tl_intg_err	6.270s	416.636us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.270s	416.636us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	50.990s	18.199ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.31406101542128070528996701756436902425963341258985491847053220106291866388392
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1195635 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[109])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1195635 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1195635 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1005])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.17783407733017441553711345931746812742806124540272584647374904459156530819328
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   8886382 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   8886382 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   8902382 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1cf555 [111001111010101010101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   8902382 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x1cf555 [111001111010101010101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])