SPI_DEVICE/2P Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.047m	39.233ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.620s	15.925us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.280s	585.666us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.680s	190.411us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.620s	1.206ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.510s	120.315us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.280s	585.666us	1	1	100.00
		spi_device_csr_aliasing	17.620s	1.206ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.580s	27.451us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.860s	70.701us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.780s	17.180us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	2.300s	47.210us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.500s	6.213us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.210s	261.452us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	4.210s	261.452us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.800s	734.038us	1	1	100.00
		spi_device_tpm_sts_read	1.860s	332.556us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.280s	11.366ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.890s	696.015us	1	1	100.00
		spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.960s	646.974us	1	1	100.00
		spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.960s	646.974us	1	1	100.00
		spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.840s	41.850us	1	1	100.00
		spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.840s	41.850us	1	1	100.00
		spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.840s	41.850us	1	1	100.00
		spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.840s	41.850us	1	1	100.00
		spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.840s	41.850us	1	1	100.00
		spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.280s	3.128ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.700s	403.909us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.700s	403.909us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.700s	403.909us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.020s	192.484us	1	1	100.00
		spi_device_read_buffer_direct	6.150s	2.886ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.700s	403.909us	1	1	100.00
		spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	3.021m	151.636ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.760s	61.652us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.760s	61.652us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.047m	39.233ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.176m	4.811ms	1	1	100.00
V2	stress_all	spi_device_stress_all	48.870s	24.307ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.780s	19.701us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.650s	16.970us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.750s	145.461us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.750s	145.461us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.620s	15.925us	1	1	100.00
		spi_device_csr_rw	3.280s	585.666us	1	1	100.00
		spi_device_csr_aliasing	17.620s	1.206ms	1	1	100.00
		spi_device_same_csr_outstanding	3.690s	269.724us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.620s	15.925us	1	1	100.00
		spi_device_csr_rw	3.280s	585.666us	1	1	100.00
		spi_device_csr_aliasing	17.620s	1.206ms	1	1	100.00
		spi_device_same_csr_outstanding	3.690s	269.724us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	2.260s	340.204us	1	1	100.00
		spi_device_tl_intg_err	10.220s	437.261us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.220s	437.261us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.043m	15.392ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.28437109020720608054915839472643139014061275527365863537580435994960285778020
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   5393216 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   5393216 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   5490216 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0xf9583e [111110010101100000111110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   5490216 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)