SRAM_CTRL/MAIN Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	42.470s	4.270ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.660s	117.375us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.590s	104.523us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.370s	151.152us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.780s	22.773us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.810s	6.897ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.590s	104.523us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	22.773us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.761m	20.219ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	50.890s	2.443ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	15.842m	82.134ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.627m	19.124ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	11.877m	64.836ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.797m	80.012ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	20.830s	10.201ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.353m	13.872ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	10.780s	857.963us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.827m	22.834ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	30.020s	1.534ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.420s	1.362ms	1	1	100.00
		sram_ctrl_throughput_w_readback	33.200s	2.114ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.400m	240.539ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.820s	714.087us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	34.974m	139.360ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.520s	17.721us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.050s	101.772us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.050s	101.772us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.660s	117.375us	1	1	100.00
		sram_ctrl_csr_rw	1.590s	104.523us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	22.773us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.800s	122.733us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.660s	117.375us	1	1	100.00
		sram_ctrl_csr_rw	1.590s	104.523us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	22.773us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.800s	122.733us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.400s	13.162ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.540s	1.461us	0	1	0.00
		sram_ctrl_tl_intg_err	2.680s	241.229us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.540s	1.461us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.680s	241.229us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.400m	240.539ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.400m	240.539ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.590s	104.523us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.353m	13.872ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.353m	13.872ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.353m	13.872ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	20.830s	10.201ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.740s	2.892ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.400s	13.162ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.460s	1.368ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	42.470s	4.270ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	42.470s	4.270ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.353m	13.872ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.540s	1.461us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	20.830s	10.201ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.540s	1.461us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.540s	1.461us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	42.470s	4.270ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.540s	1.461us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.070s	230.727us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.42293163897476913341385575438855782265102764201312857252025703888156977228862
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1368049425 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x70) != exp (0x5e)
        UVM_INFO @ 1368049425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.86426965254825317893975590663749445683008474536083776830232560739835938329977
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1461065 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1461065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---