SRAM_CTRL/RET Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	5.090s	111.224us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.550s	13.808us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.690s	43.446us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.860s	54.762us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.560s	24.018us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.340s	390.341us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.690s	43.446us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	24.018us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.460s	2.245ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.060s	104.193us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.359m	20.718ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.438m	2.826ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	40.790s	2.491ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.199m	1.416ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.120s	1.910ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.999m	8.030ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	52.730s	4.749ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.650m	23.424ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.028m	722.777us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	20.420s	199.688us	1	1	100.00
		sram_ctrl_throughput_w_readback	24.510s	1.910ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.638m	23.996ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.760s	27.397us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	27.820m	35.577ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.660s	46.025us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.510s	33.042us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.510s	33.042us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.550s	13.808us	1	1	100.00
		sram_ctrl_csr_rw	1.690s	43.446us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	24.018us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.670s	26.388us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.550s	13.808us	1	1	100.00
		sram_ctrl_csr_rw	1.690s	43.446us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	24.018us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.670s	26.388us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.300s	391.553us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.590s	15.921us	0	1	0.00
		sram_ctrl_tl_intg_err	3.090s	1.087ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.590s	15.921us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.090s	1.087ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.638m	23.996ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.638m	23.996ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.690s	43.446us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.999m	8.030ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.999m	8.030ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.999m	8.030ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.120s	1.910ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.970s	36.444us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.300s	391.553us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.780s	37.843us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	5.090s	111.224us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	5.090s	111.224us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.999m	8.030ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.590s	15.921us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.120s	1.910ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.590s	15.921us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.590s	15.921us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	5.090s	111.224us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.590s	15.921us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.347m	25.122ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.28484238071009291565123127743578424233267653327322156592066132532344657706471
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  15921331 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  15921331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---