SYSRST_CTRL Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 3.470s 2.141ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.180s 2.515ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.550s 2.276ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.910s 2.274ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 5.630s 4.034ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 5.610s 2.053ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 9.460s 2.943ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 5.150s 3.218ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.140s 2.035ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 5.610s 2.053ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.150s 3.218ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.849m 112.737ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 20.700s 29.352ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 6.647m 241.778ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 9.180s 4.696ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 6.460s 2.510ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 4.860s 2.209ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 4.060s 3.988ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.540s 2.635ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 4.120s 2.436ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.340m 40.276ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 7.550s 13.470ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 3.130s 2.027ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.170s 2.068ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.180s 2.164ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.180s 2.164ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 5.630s 4.034ms 1 1 100.00
sysrst_ctrl_csr_rw 5.610s 2.053ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.150s 3.218ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 17.230s 7.495ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 5.630s 4.034ms 1 1 100.00
sysrst_ctrl_csr_rw 5.610s 2.053ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.150s 3.218ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 17.230s 7.495ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 22.530s 22.038ms 1 1 100.00
sysrst_ctrl_tl_intg_err 41.970s 22.222ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 41.970s 22.222ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 8.610s 22.351ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00