UART Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: 1a62881

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	3.080s	667.734us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.520s	47.942us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.510s	20.151us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.270s	538.095us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.740s	27.972us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.630s	213.563us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.510s	20.151us	1	1	100.00
		uart_csr_aliasing	1.740s	27.972us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	50.660s	40.263ms	1	1	100.00
V2	parity	uart_smoke	3.080s	667.734us	1	1	100.00
		uart_tx_rx	50.660s	40.263ms	1	1	100.00
V2	parity_error	uart_intr	56.780s	66.630ms	1	1	100.00
		uart_rx_parity_err	18.410s	36.701ms	1	1	100.00
V2	watermark	uart_tx_rx	50.660s	40.263ms	1	1	100.00
		uart_intr	56.780s	66.630ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.400m	108.713ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	56.640s	208.219ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	18.370s	9.797ms	1	1	100.00
V2	rx_frame_err	uart_intr	56.780s	66.630ms	1	1	100.00
V2	rx_break_err	uart_intr	56.780s	66.630ms	1	1	100.00
V2	rx_timeout	uart_intr	56.780s	66.630ms	1	1	100.00
V2	perf	uart_perf	1.441m	14.747ms	1	1	100.00
V2	sys_loopback	uart_loopback	10.030s	5.517ms	1	1	100.00
V2	line_loopback	uart_loopback	10.030s	5.517ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.389m	63.766ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.280s	2.267ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.070s	994.394us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	36.640s	5.771ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	13.108m	114.573ms	1	1	100.00
V2	stress_all	uart_stress_all	1.971m	77.692ms	1	1	100.00
V2	alert_test	uart_alert_test	2.040s	21.118us	1	1	100.00
V2	intr_test	uart_intr_test	1.590s	13.214us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.330s	310.192us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.330s	310.192us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.520s	47.942us	1	1	100.00
		uart_csr_rw	1.510s	20.151us	1	1	100.00
		uart_csr_aliasing	1.740s	27.972us	1	1	100.00
		uart_same_csr_outstanding	2.080s	46.672us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.520s	47.942us	1	1	100.00
		uart_csr_rw	1.510s	20.151us	1	1	100.00
		uart_csr_aliasing	1.740s	27.972us	1	1	100.00
		uart_same_csr_outstanding	2.080s	46.672us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.950s	1.001ms	1	1	100.00
		uart_tl_intg_err	1.920s	51.800us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.920s	51.800us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	49.730s	5.619ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00