CHIP Simulation Results

Monday May 05 2025 18:41:16 UTC

GitHub Revision: `1a62881`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.083m	3.282ms	1	1	100.00
		chip_sw_example_rom	1.201m	2.124ms	1	1	100.00
		chip_sw_example_manufacturer	1.600m	2.067ms	1	1	100.00
		chip_sw_example_concurrency	1.967m	2.639ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.530m	7.334ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.421m	4.375ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	33.634m	31.066ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	54.790m	30.129ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	50.900s	2.952ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	54.790m	30.129ms	1	1	100.00
		chip_csr_rw	3.421m	4.375ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.760s	223.663us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.323m	4.273ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.323m	4.273ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.323m	4.273ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.000m	4.112ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.000m	4.112ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.435m	3.512ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.777m	4.440ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	4.966m	4.004ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	27.992m	12.939ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	6.542m	4.041ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.231m	8.142ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.300m	5.004ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.300m	5.004ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.011m	2.858ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.849m	6.158ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.122m	2.905ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	7.951m	7.947ms	1	1	100.00
		chip_tap_straps_testunlock0	4.073m	4.350ms	1	1	100.00
		chip_tap_straps_rma	4.108m	4.973ms	1	1	100.00
		chip_tap_straps_prod	14.182m	14.672ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.574m	2.979ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.624m	8.521ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.354m	6.048ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.354m	6.048ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.651m	8.092ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	37.437m	24.151ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.522m	3.866ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.454m	5.464ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.580m	18.196ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.451m	2.969ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.523m	6.810ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.922m	3.057ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.331m	12.375ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.138m	2.711ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	7.348m	5.762ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.483m	2.618ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.369m	3.429ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.082m	6.188ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.848m	4.971ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.452m	2.303ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.848m	4.971ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.255m	2.701ms	1	1	100.00
		chip_sw_aes_smoketest	2.135m	2.517ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.504m	2.722ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.583m	3.103ms	1	1	100.00
		chip_sw_csrng_smoketest	3.153m	3.442ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.696m	2.911ms	1	1	100.00
		chip_sw_gpio_smoketest	2.934m	2.543ms	1	1	100.00
		chip_sw_hmac_smoketest	3.058m	3.647ms	1	1	100.00
		chip_sw_kmac_smoketest	2.687m	2.455ms	1	1	100.00
		chip_sw_otbn_smoketest	17.350m	9.995ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.115m	5.469ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.493m	5.546ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.284m	2.728ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.233m	3.108ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.011m	2.695ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.238m	2.814ms	1	1	100.00
		chip_sw_uart_smoketest	2.624m	2.940ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.914m	2.663ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.493m	4.656ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.973h	60.951ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	38.109m	15.046ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.393m	6.074ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.964m	3.357ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.589m	3.535ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.833h	54.175ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.887h	57.845ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	56.020s	2.186ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	56.020s	2.186ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	54.790m	30.129ms	1	1	100.00
		chip_same_csr_outstanding	33.938m	26.633ms	1	1	100.00
		chip_csr_hw_reset	3.530m	7.334ms	1	1	100.00
		chip_csr_rw	3.421m	4.375ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	54.790m	30.129ms	1	1	100.00
		chip_same_csr_outstanding	33.938m	26.633ms	1	1	100.00
		chip_csr_hw_reset	3.530m	7.334ms	1	1	100.00
		chip_csr_rw	3.421m	4.375ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	15.330s	267.705us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.230s	49.559us	1	1	100.00
		xbar_smoke_large_delays	54.990s	9.105ms	1	1	100.00
		xbar_smoke_slow_rsp	58.340s	6.300ms	1	1	100.00
		xbar_random_zero_delays	11.260s	182.572us	1	1	100.00
		xbar_random_large_delays	33.920s	5.645ms	1	1	100.00
		xbar_random_slow_rsp	1.410m	9.712ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	7.470s	177.299us	1	1	100.00
		xbar_error_and_unmapped_addr	18.960s	298.906us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	8.210s	281.313us	1	1	100.00
		xbar_error_and_unmapped_addr	18.960s	298.906us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	5.390s	64.181us	1	1	100.00
		xbar_access_same_device_slow_rsp	34.040s	3.083ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	15.380s	765.992us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.410m	7.411ms	1	1	100.00
		xbar_stress_all_with_error	1.698m	2.425ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.672m	1.435ms	1	1	100.00
		xbar_stress_all_with_reset_error	4.659m	5.234ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.109m	15.046ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.120m	22.981ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.701m	15.268ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.263m	10.701ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.086m	16.301ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.569m	15.178ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.868m	15.469ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.600m	14.766ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	30.110s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	31.280s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.590s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.710s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.890s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	28.460s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	31.540s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	27.110s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.630s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	26.790s	10.380us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.290s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.220s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	27.130s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.080s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.320s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.300s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.220s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.530s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.790s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.110s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.940s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.400s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.720s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.350s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	29.380s	10.200us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.390m	11.423ms	1	1	100.00
		rom_e2e_asm_init_dev	39.307m	15.753ms	1	1	100.00
		rom_e2e_asm_init_prod	35.727m	15.410ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.080m	15.221ms	1	1	100.00
		rom_e2e_asm_init_rma	37.119m	14.328ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	37.137m	15.339ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.832m	15.250ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	34.463m	15.355ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.188m	14.842ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.899m	34.591ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.899m	34.591ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.990m	2.466ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.451m	2.969ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.758m	2.658ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.648m	2.855ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.339m	9.059ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.104m	2.711ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.450m	5.290ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.163m	5.073ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.056m	5.917ms	1	1	100.00
		chip_plic_all_irqs_10	4.332m	3.579ms	1	1	100.00
		chip_plic_all_irqs_20	5.705m	4.854ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.768m	3.600ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.040m	10.953ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.299m	4.285ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.581m	2.057ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.205m	10.807ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.810m	6.471ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.807m	7.732ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.142m	8.301ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.897h	256.046ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.234m	3.401ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.115m	5.469ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.234m	3.401ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.252m	9.398ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.252m	9.398ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.849m	7.518ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.500m	5.381ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.711m	5.758ms	1	1	100.00
		chip_sw_aes_idle	2.648m	2.855ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.823m	2.944ms	1	1	100.00
		chip_sw_kmac_idle	2.321m	3.305ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.339m	3.628ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.087m	4.256ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.604m	4.336ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.855m	3.404ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.941m	11.887ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.865m	3.943ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.523m	4.447ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.403m	4.452ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.765m	4.555ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.218m	3.528ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.139m	4.697ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.651m	8.092ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.011m	5.764ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.403m	4.452ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.765m	4.555ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.522m	3.866ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.454m	5.464ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.580m	18.196ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.451m	2.969ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.523m	6.810ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.922m	3.057ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.331m	12.375ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.138m	2.711ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	7.348m	5.762ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.483m	2.618ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.112m	2.654ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.781m	4.927ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.839m	7.610ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	46.365m	23.592ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.752m	2.739ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.328m	3.066ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	19.763m	13.218ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.904m	3.315ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.740m	4.600ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.114m	25.378ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.729h	173.081ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.651m	8.092ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.548m	4.586ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.750m	3.191ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.163m	5.073ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	12.810m	6.471ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.778m	6.358ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	5.016m	4.778ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.273m	7.640ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.095m	2.654ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	41.694m	15.949ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.740m	3.762ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.091m	5.914ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.740m	3.762ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.778m	6.358ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	3.023m	2.459ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	21.417m	23.483ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.844m	5.381ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.454m	5.464ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.983m	3.513ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.522m	3.866ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.016h	44.324ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	21.417m	23.483ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.821m	3.557ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	11.145m	7.048ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.251m	5.354ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.016h	44.324ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.251m	5.354ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.251m	5.354ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.251m	5.354ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.251m	5.354ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.163m	5.073ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.067m	4.163ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.532m	5.725ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.252m	4.853ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.252m	4.853ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.069m	2.296ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.922m	3.057ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.823m	2.944ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.047m	3.087ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	14.002m	6.774ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.245m	4.165ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	8.058m	6.033ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.099m	4.464ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.895m	4.120ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	11.145m	7.048ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.331m	12.375ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	9.610m	6.112ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.339m	9.059ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	27.411m	10.389ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.503m	2.562ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.439m	3.056ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.138m	2.711ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	11.145m	7.048ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.210m	6.094ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.876m	2.700ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	21.137m	10.767ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.321m	3.305ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.450m	5.290ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	7.951m	7.947ms	1	1	100.00
		chip_tap_straps_rma	4.108m	4.973ms	1	1	100.00
		chip_tap_straps_prod	14.182m	14.672ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.838m	2.744ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.210m	6.094ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.210m	6.094ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.210m	6.094ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	25.516m	11.893ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.251m	5.354ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.016h	44.324ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.246m	3.772ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.153m	7.252ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.054m	7.485ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.663m	5.588ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.210m	6.094ms	1	1	100.00
		chip_sw_keymgr_key_derivation	11.145m	7.048ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	6.364m	8.742ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.302m	9.003ms	1	1	100.00
		chip_prim_tl_access	1.067m	4.163ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.011m	5.764ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.865m	3.943ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.523m	4.447ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.403m	4.452ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.765m	4.555ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.218m	3.528ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.139m	4.697ms	1	1	100.00
		chip_tap_straps_dev	7.951m	7.947ms	1	1	100.00
		chip_tap_straps_rma	4.108m	4.973ms	1	1	100.00
		chip_tap_straps_prod	14.182m	14.672ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.952m	18.857ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.600m	3.037ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.665m	3.088ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.894m	3.888ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.369m	3.286ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.421m	31.227ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.952m	18.857ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.051h	51.671ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.017h	48.213ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.618m	9.055ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	57.997m	48.813ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.421m	31.227ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.178m	2.635ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.367m	2.484ms	1	1	100.00
		rom_volatile_raw_unlock	1.140m	2.624ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	51.532m	17.034ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.580m	18.196ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.711m	5.758ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.711m	5.758ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.711m	5.758ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.370m	3.944ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.210m	6.094ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	21.417m	23.483ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.370m	3.944ms	1	1	100.00
		chip_sw_keymgr_key_derivation	11.145m	7.048ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.951m	5.715ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.396m	2.416ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	21.417m	23.483ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.370m	3.944ms	1	1	100.00
		chip_sw_keymgr_key_derivation	11.145m	7.048ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.951m	5.715ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.396m	2.416ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.210m	6.094ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.628m	4.692ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.838m	2.744ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.246m	3.772ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.153m	7.252ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.054m	7.485ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.663m	5.588ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.210m	6.094ms	1	1	100.00
		chip_prim_tl_access	1.067m	4.163ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.067m	4.163ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.992m	9.542ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.951m	6.929ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	12.985m	24.887ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.429m	7.255ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	8.054m	8.427ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	7.199m	7.332ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	18.759m	22.850ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.489m	11.681ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.252m	9.398ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	14.591m	10.290ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.588m	5.026ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.951m	6.929ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.770m	4.786ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	31.305m	30.024ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.661m	6.834ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.844m	5.476ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.881m	29.092ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	2.834m	2.436ms	0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs	16.112m	9.699ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	18.927m	18.428ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.858m	2.145ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.163m	5.073ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.364m	8.742ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.364m	8.742ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	16.112m	9.699ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.881m	29.092ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.588m	5.026ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.115m	5.469ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	2.668m	4.029ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.460m	4.690ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.706m	5.143ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.040m	10.953ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.859m	2.242ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.163m	5.073ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.807m	7.732ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.606m	4.681ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.986m	4.644ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.866m	3.753ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.396m	2.416ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.460m	4.690ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.460m	4.690ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	14.640m	10.169ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.940m	13.492ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	2.668m	4.029ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.353m	4.051ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.341m	6.248ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.108m	4.973ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.952m	18.857ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.056m	5.917ms	1	1	100.00
		chip_plic_all_irqs_10	4.332m	3.579ms	1	1	100.00
		chip_plic_all_irqs_20	5.705m	4.854ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.992m	2.293ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.534m	2.937ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	38.109m	15.046ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.461m	6.384ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.750m	3.012ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.977m	3.145ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.342m	2.685ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.951m	5.715ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	7.348m	5.762ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.814m	7.599ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.434m	6.727ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.302m	9.003ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.163m	5.073ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.354m	6.048ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	2.834m	2.436ms	0	1	0.00
		chip_sw_sysrst_ctrl_reset	17.046m	25.123ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.431m	3.151ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	4.043m	3.846ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.599m	4.664ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.046m	25.123ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.046m	25.123ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	2.570m	2.668ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	2.570m	2.668ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	5.250m	6.399ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.899m	34.591ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.203m	3.219ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.635m	2.669ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.655m	3.803ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.715m	3.444ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.986m	8.359ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.263h	31.999ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	27.848m	12.451ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.979m	2.560ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.841m	3.202ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.754m	2.728ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.458h	71.377ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.972m	3.658ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.927m	10.744ms	1	1	100.00
		rom_e2e_jtag_debug_dev	14.771m	10.701ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.761m	11.705ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.148m	4.383ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.513m	4.454ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.086m	4.228ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	19.084s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.560m	5.282ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.326m	2.775ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	9.837m	4.522ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	13.763m	7.713ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.111m	2.731ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.710m	4.865ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	58.200s	2.066ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.063m	4.989ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.865m	5.684ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.037m	4.192ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	16.112m	9.699ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.927m	10.744ms	1	1	100.00
		rom_e2e_jtag_debug_dev	14.771m	10.701ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.761m	11.705ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.956m	5.542ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.163m	5.073ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.334h	38.528ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.334h	38.528ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.769m	3.406ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.000m	4.112ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	51.047m	19.357ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.408m	3.070ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.751m	4.826ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.474m	2.784ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.934m	3.523ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.303m	3.306ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.721s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.018m	2.735ms	1	1	100.00
		TOTAL			283	325	87.08

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.78802730833284043360700935423844640791835283317836480550090502777365278352832
    Line 611, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.99113051793070753568904695697368155791385560794646772609203832590528642525429
    Line 606, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.114326650528165040014711350916878169608292482115285163813260618824859697447642
    Line 682, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.18869079655618680833493089550585894179035755633057038767925622182861628535131
    Line 647, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.13086051364305979626216882996057692042782946275800358145459493218456066355474
    Line 699, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.48923079278123681545237108026350344586913546799307288182638356150654276809906
    Line 509, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.52463678394144210075811779311046051760467557481622957500329765904942254964594
    Line 566, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.115390510552565971655691005281865190816261397928279553706674605943787844157735
    Line 595, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.54374967898048773392675495624010173472119192600118013793578583090881850076867
    Line 594, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.114671728682601226336364208468804192604893390345305160427791880462144769530802
    Line 649, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.24113242949527064337370581881412279243717332703366333511045022647115032678029
    Line 753, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.61396792022559217493111651542751968088689540894331226691919278132931105604283
    Line 657, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1389623170373956379260229385765078764991604141414691679024700655853760665968
    Line 751, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.103763710662319853957084072800911948847567189257455526497630954148555057809262
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 1.601s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.21807969182956578505562502262479349206804233275329404269357363126582287757070
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 8.611s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.32992579701698351372548016404702556850304419827328803624715143863827588855271
    Line 766, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.85442925618837311245790814187088542381516519586348848504703503433397138990483
    Line 621, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.61288594507372390066920333163287949752654034747397973670971147273452454884714
    Line 764, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.32541544172918108913754727654814365691884469618347147979587388454779690680299
    Line 711, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.85713375365901871789472113074263032670167013386141157727593977707666485631429
    Line 440, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3011.593118 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3011.593118 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98029) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.53271400349362850188885844838116114782029754477701322327312948884135227009931
Line 432, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4690.208926 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98029) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4690.208926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:43)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns * has 1 failures:
- Test chip_sw_pwrmgr_sysrst_ctrl_reset has 1 failures.
  - 0.chip_sw_pwrmgr_sysrst_ctrl_reset.62234760111929486576687631522656531387307230191104953991432119689876364587093
    Line 421, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest/run.log
```
  UVM_ERROR @ 2436.147920 us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:43)] DIF-fail: dif_pwrmgr_set_request_sources(pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns 3
  UVM_INFO @ 2436.147920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:134)] DIF-fail: dif_pwrmgr_set_request_sources(&pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns * has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.61926171066233976210347372527138267886935002626860575171275648079612953845337
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 2668.392500 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:134)] DIF-fail: dif_pwrmgr_set_request_sources(&pwrmgr, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne, kDifToggleEnabled) returns 3
  UVM_INFO @ 2668.392500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.5951244136516776670525851896838992822277227643103945709653470592475441269990
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34590.728816 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34590.728816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.72640538736796057016760063194026114821394476818243781018748248383672221331817
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2710.977120 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2710.977120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.104222588636328519247551856737566824120091944840344501967731912823378271877932
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2056.872224 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2056.872224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41631) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.101529275664104170197107491023046486195910613732735069098189654707850754948900
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2186.038468 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41631) { a_addr: 'h104c8  a_data: 'h73c3a2a6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h4  a_user: 'h19957  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2186.038468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.2481249778317845796199471440011038930520935354922085459106504926228476501442
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3305.503808 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3305.503808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.13500786571128420242870290978533332710499292627319507157342026852628114732976
    Line 421, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2728.159144 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2728.159144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.42372063078721696079548299354355317268751681607293777011285238420700426177507
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3357.440500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3357.440500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.95232977391436958948059892355746805806190132613060161514565820054983846649760
    Line 431, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3534.570000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3534.570000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.66495106993236263755086283203547373784740002264241399512533163811402972333160
    Line 442, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 24151.351354 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 24151.351354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.96835486263173933214439563840563304943185048012950519654598878045389852105284
    Line 469, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3658.470134 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3658.470134 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.43893221758002995056565823577192718825022274027190072189183606312001877352864
    Line 748, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.24820727756317662270421913465653755057479558276729881418102354189879440968256
    Line 611, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31843) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.104585033048086076384736648526907032418211516669802385374328548423961766684049
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2952.031608 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31843) { a_addr: 'h10480  a_data: 'h148715b2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h4  a_user: 'h1a509  d_param: 'h0  d_source: 'h37  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2952.031608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---