ADC_CTRL Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	2.770s	5.964ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.290s	975.092us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.190s	465.516us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	59.760s	49.551ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.910s	677.995us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.240s	574.265us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.190s	465.516us	1	1	100.00
		adc_ctrl_csr_aliasing	2.910s	677.995us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	8.803m	335.478ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.358m	166.547ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.606m	169.633ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	57.870s	162.032ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	17.019m	555.814ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.171m	400.623ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	50.020s	167.462ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.106m	164.040ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.380s	3.339ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.208m	41.113ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.149m	91.976ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	34.940s	32.799ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.960s	591.428us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.950s	370.996us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.700s	350.198us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.700s	350.198us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.290s	975.092us	1	1	100.00
		adc_ctrl_csr_rw	2.190s	465.516us	1	1	100.00
		adc_ctrl_csr_aliasing	2.910s	677.995us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.580s	3.021ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.290s	975.092us	1	1	100.00
		adc_ctrl_csr_rw	2.190s	465.516us	1	1	100.00
		adc_ctrl_csr_aliasing	2.910s	677.995us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.580s	3.021ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	5.170s	4.325ms	1	1	100.00
		adc_ctrl_tl_intg_err	13.420s	8.237ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	13.420s	8.237ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.610s	4.159ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00