EDN Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.000s 16.135us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.840s 48.992us 1 1 100.00
V1 csr_rw edn_csr_rw 2.190s 13.775us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.470s 1.277ms 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 2.950s 188.378us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.360s 108.336us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.190s 13.775us 1 1 100.00
edn_csr_aliasing 2.950s 188.378us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.940s 102.675us 1 1 100.00
V2 csrng_commands edn_genbits 1.940s 102.675us 1 1 100.00
V2 genbits edn_genbits 1.940s 102.675us 1 1 100.00
V2 interrupts edn_intr 1.980s 28.486us 1 1 100.00
V2 alerts edn_alert 2.300s 103.626us 1 1 100.00
V2 errs edn_err 1.910s 25.696us 1 1 100.00
V2 disable edn_disable 1.570s 41.869us 1 1 100.00
edn_disable_auto_req_mode 1.880s 76.031us 1 1 100.00
V2 stress_all edn_stress_all 4.050s 1.069ms 1 1 100.00
V2 intr_test edn_intr_test 2.240s 22.870us 1 1 100.00
V2 alert_test edn_alert_test 1.860s 38.553us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.350s 55.038us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.350s 55.038us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.840s 48.992us 1 1 100.00
edn_csr_rw 2.190s 13.775us 1 1 100.00
edn_csr_aliasing 2.950s 188.378us 1 1 100.00
edn_same_csr_outstanding 2.050s 92.719us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.840s 48.992us 1 1 100.00
edn_csr_rw 2.190s 13.775us 1 1 100.00
edn_csr_aliasing 2.950s 188.378us 1 1 100.00
edn_same_csr_outstanding 2.050s 92.719us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.120s 239.943us 1 1 100.00
edn_tl_intg_err 2.740s 187.392us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 2.070s 16.778us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.300s 103.626us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.120s 239.943us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.120s 239.943us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.120s 239.943us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.120s 239.943us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.300s 103.626us 1 1 100.00
edn_sec_cm 4.120s 239.943us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.300s 103.626us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.740s 187.392us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets