| V1 |
smoke |
hmac_smoke |
11.100s |
331.327us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
hmac_csr_hw_reset |
1.660s |
36.972us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
hmac_csr_rw |
1.560s |
22.375us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
hmac_csr_bit_bash |
5.070s |
2.093ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
hmac_csr_aliasing |
3.180s |
319.433us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
hmac_csr_mem_rw_with_rand_reset |
2.270s |
21.830us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
hmac_csr_rw |
1.560s |
22.375us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
3.180s |
319.433us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
long_msg |
hmac_long_msg |
20.990s |
1.695ms |
1 |
1 |
100.00 |
| V2 |
back_pressure |
hmac_back_pressure |
42.910s |
2.980ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
hmac_test_sha256_vectors |
2.694m |
10.853ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.886m |
164.535ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.445m |
66.968ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
9.690s |
381.464us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
7.750s |
951.519us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
10.790s |
3.889ms |
1 |
1 |
100.00 |
| V2 |
burst_wr |
hmac_burst_wr |
7.490s |
3.616ms |
1 |
1 |
100.00 |
| V2 |
datapath_stress |
hmac_datapath_stress |
5.602m |
4.695ms |
1 |
1 |
100.00 |
| V2 |
error |
hmac_error |
32.220s |
1.665ms |
1 |
1 |
100.00 |
| V2 |
wipe_secret |
hmac_wipe_secret |
1.078m |
3.243ms |
1 |
1 |
100.00 |
| V2 |
save_and_restore |
hmac_smoke |
11.100s |
331.327us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
20.990s |
1.695ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
42.910s |
2.980ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
5.602m |
4.695ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
7.490s |
3.616ms |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
20.475m |
162.661ms |
1 |
1 |
100.00 |
| V2 |
fifo_empty_status_interrupt |
hmac_smoke |
11.100s |
331.327us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
20.990s |
1.695ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
42.910s |
2.980ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
5.602m |
4.695ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.078m |
3.243ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
2.694m |
10.853ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.886m |
164.535ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.445m |
66.968ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
9.690s |
381.464us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
7.750s |
951.519us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
10.790s |
3.889ms |
1 |
1 |
100.00 |
| V2 |
wide_digest_configurable_key_length |
hmac_smoke |
11.100s |
331.327us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
20.990s |
1.695ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
42.910s |
2.980ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
5.602m |
4.695ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
7.490s |
3.616ms |
1 |
1 |
100.00 |
|
|
hmac_error |
32.220s |
1.665ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.078m |
3.243ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
2.694m |
10.853ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.886m |
164.535ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.445m |
66.968ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
9.690s |
381.464us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
7.750s |
951.519us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
10.790s |
3.889ms |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
20.475m |
162.661ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
hmac_stress_all |
20.475m |
162.661ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
hmac_alert_test |
1.440s |
12.335us |
1 |
1 |
100.00 |
| V2 |
intr_test |
hmac_intr_test |
1.560s |
14.459us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
hmac_tl_errors |
3.060s |
562.259us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
hmac_tl_errors |
3.060s |
562.259us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
hmac_csr_hw_reset |
1.660s |
36.972us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.560s |
22.375us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
3.180s |
319.433us |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
2.080s |
124.716us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
hmac_csr_hw_reset |
1.660s |
36.972us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.560s |
22.375us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
3.180s |
319.433us |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
2.080s |
124.716us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
17 |
17 |
100.00 |
| V2S |
tl_intg_err |
hmac_sec_cm |
1.600s |
40.753us |
1 |
1 |
100.00 |
|
|
hmac_tl_intg_err |
2.300s |
352.907us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
hmac_tl_intg_err |
2.300s |
352.907us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
write_config_and_secret_key_during_msg_wr |
hmac_smoke |
11.100s |
331.327us |
1 |
1 |
100.00 |
| V3 |
stress_reset |
hmac_stress_reset |
2.680s |
106.187us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
hmac_stress_all_with_rand_reset |
4.136m |
4.301ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
hmac_directed |
1.910s |
40.370us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
28 |
28 |
100.00 |