I2C Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: `b6a2634`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	40.970s	2.903ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.640s	1.008ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.620s	21.960us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.640s	29.328us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.800s	66.360us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.480s	350.792us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.720s	30.095us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.640s	29.328us	1	1	100.00
		i2c_csr_aliasing	2.480s	350.792us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.260s	113.454us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	54.047m	35.165ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.170s	468.564us	1	1	100.00
V2	host_override	i2c_host_override	1.600s	100.627us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.467m	3.780ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	48.470s	11.022ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.730s	66.720us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.540s	279.561us	1	1	100.00
		i2c_host_fifo_reset_rx	3.550s	307.153us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	27.690s	4.008ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	14.280s	481.131us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.710s	26.051us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.450s	1.958ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	17.610s	9.784ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.770s	2.288ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	9.710s	1.366ms	1	1	100.00
		i2c_target_intr_smoke	5.660s	1.235ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.730s	392.086us	1	1	100.00
		i2c_target_fifo_reset_tx	1.740s	136.908us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	5.876m	44.522ms	1	1	100.00
		i2c_target_stress_rd	9.710s	1.366ms	1	1	100.00
		i2c_target_intr_stress_wr	1.208m	20.413ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.370s	5.265ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.960s	10.045ms	0	1	0.00
V2	bad_address	i2c_target_bad_addr	4.910s	2.017ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.210s	1.916ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.780s	2.842ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.880s	511.945us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.170s	468.564us	1	1	100.00
		i2c_host_perf_precise	15.640s	2.438ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	14.280s	481.131us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.030s	134.298us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.610s	451.716us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.600s	2.292ms	1	1	100.00
		i2c_target_nack_txstretch	2.030s	493.401us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	12.410s	461.734us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.590s	462.524us	1	1	100.00
V2	alert_test	i2c_alert_test	1.480s	45.049us	1	1	100.00
V2	intr_test	i2c_intr_test	1.620s	19.886us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.490s	147.532us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.490s	147.532us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.620s	21.960us	1	1	100.00
		i2c_csr_rw	1.640s	29.328us	1	1	100.00
		i2c_csr_aliasing	2.480s	350.792us	1	1	100.00
		i2c_same_csr_outstanding	1.940s	99.225us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.620s	21.960us	1	1	100.00
		i2c_csr_rw	1.640s	29.328us	1	1	100.00
		i2c_csr_aliasing	2.480s	350.792us	1	1	100.00
		i2c_same_csr_outstanding	1.940s	99.225us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.460s	602.564us	1	1	100.00
		i2c_sec_cm	1.690s	169.963us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.460s	602.564us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	29.850s	20.398ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.720s	49.575us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	2.720s	153.518us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.22358868726804036679959122566386526171755871735172249820750871484237711046289
    Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20398259642 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20398259642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.114922778324971859182192222160189068438987008159689225637521081101727624862449
    Line 86, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 153518392 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 153518392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.76561862781967212956979126723605257932545615186148029933393007543960510096077
Line 199, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 35165051407 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @38094858

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:
- Test i2c_target_stretch has 1 failures.
  - 0.i2c_target_stretch.113514970239027557449742553198544136989070149695631506205078998567656645294410
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10045225750 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10045225750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.66311340335224454173832180550734078673532038736211446480340404480785813480688
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  49575104 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  49575104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.52946835055413589758556314236083604626781664691253335858774158016116245365863
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_ERROR @  26051278 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------
```