KEYMGR Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.340s	82.751us	1	1	100.00
V1	random	keymgr_random	5.460s	192.605us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.810s	35.768us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.640s	16.980us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	1.910s	265.197us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	11.150s	1.459ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.060s	16.209us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.640s	16.980us	1	1	100.00
		keymgr_csr_aliasing	11.150s	1.459ms	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	36.220s	6.374ms	1	1	100.00
V2	sideload	keymgr_sideload	2.700s	57.187us	1	1	100.00
		keymgr_sideload_kmac	4.160s	194.792us	1	1	100.00
		keymgr_sideload_aes	2.890s	129.303us	1	1	100.00
		keymgr_sideload_otbn	4.320s	433.619us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.290s	124.978us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.780s	64.144us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.400s	142.406us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	20.310s	2.084ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.660s	59.296us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.190s	49.011us	1	1	100.00
V2	stress_all	keymgr_stress_all	1.981m	10.683ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.620s	21.386us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.740s	11.000us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.820s	164.357us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.820s	164.357us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.810s	35.768us	1	1	100.00
		keymgr_csr_rw	1.640s	16.980us	1	1	100.00
		keymgr_csr_aliasing	11.150s	1.459ms	1	1	100.00
		keymgr_same_csr_outstanding	2.070s	26.294us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.810s	35.768us	1	1	100.00
		keymgr_csr_rw	1.640s	16.980us	1	1	100.00
		keymgr_csr_aliasing	11.150s	1.459ms	1	1	100.00
		keymgr_same_csr_outstanding	2.070s	26.294us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
		keymgr_tl_intg_err	2.670s	37.128us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.290s	129.842us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.290s	129.842us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.290s	129.842us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.290s	129.842us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.320s	253.969us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.670s	37.128us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.290s	129.842us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	36.220s	6.374ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	5.460s	192.605us	1	1	100.00
		keymgr_csr_rw	1.640s	16.980us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	5.460s	192.605us	1	1	100.00
		keymgr_csr_rw	1.640s	16.980us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	5.460s	192.605us	1	1	100.00
		keymgr_csr_rw	1.640s	16.980us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.780s	64.144us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.660s	59.296us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.660s	59.296us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	5.460s	192.605us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.760s	63.002us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	10.550s	429.019us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.780s	64.144us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	10.550s	429.019us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	10.550s	429.019us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	10.550s	429.019us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.850s	1.162ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	10.550s	429.019us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.800s	1.709ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.71075742090169461536069804168862003887725207327146150675638518448738920831790
      Line 104, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
        UVM_ERROR @  37128096 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
        UVM_INFO @  37128096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.1646318543730280574621841247368967703233094603747970813122226008632397409437
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
        UVM_ERROR @ 265197366 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] sealing_sw_binding_7_rd_A
        UVM_INFO @ 265197366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.44478521960369394675654983487400858383247969748233488322582558277620997071214
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
        UVM_ERROR @  26294219 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
        UVM_INFO @  26294219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.27075378192273425396783642973597931429468012732219661067222116826804240487552
      Line 1089, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1709011154 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1709011154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---