KMAC/MASKED Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	39.500s	9.917ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.820s	82.980us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.750s	91.917us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.900s	1.849ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.860s	1.447ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.410s	109.799us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.750s	91.917us	1	1	100.00
		kmac_csr_aliasing	6.860s	1.447ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.610s	13.700us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.160s	69.883us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	37.791m	386.154ms	1	1	100.00
V2	burst_write	kmac_burst_write	13.999m	40.585ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.120s	1.308ms	1	1	100.00
		kmac_test_vectors_sha3_256	31.680s	5.862ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.230s	5.922ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.780s	3.812ms	1	1	100.00
		kmac_test_vectors_shake_128	3.103m	16.235ms	1	1	100.00
		kmac_test_vectors_shake_256	1.833m	14.653ms	1	1	100.00
		kmac_test_vectors_kmac	3.160s	107.397us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.450s	692.034us	1	1	100.00
V2	sideload	kmac_sideload	6.930s	637.258us	1	1	100.00
V2	app	kmac_app	2.813m	9.112ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.234m	16.708ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.255m	8.036ms	1	1	100.00
V2	error	kmac_error	2.119m	4.636ms	1	1	100.00
V2	key_error	kmac_key_error	2.030s	46.229us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.860s	79.203us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.850s	30.703us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.800s	18.363us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	36.770s	85.662ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	4.090s	136.616us	1	1	100.00
V2	stress_all	kmac_stress_all	4.343m	172.894ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.660s	55.059us	1	1	100.00
V2	alert_test	kmac_alert_test	1.620s	172.468us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.010s	50.056us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.010s	50.056us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.820s	82.980us	1	1	100.00
		kmac_csr_rw	1.750s	91.917us	1	1	100.00
		kmac_csr_aliasing	6.860s	1.447ms	1	1	100.00
		kmac_same_csr_outstanding	2.140s	27.276us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.820s	82.980us	1	1	100.00
		kmac_csr_rw	1.750s	91.917us	1	1	100.00
		kmac_csr_aliasing	6.860s	1.447ms	1	1	100.00
		kmac_same_csr_outstanding	2.140s	27.276us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.690s	100.076us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.690s	100.076us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.690s	100.076us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.690s	100.076us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.280s	789.735us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.251m	35.531ms	1	1	100.00
		kmac_tl_intg_err	3.850s	123.898us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.850s	123.898us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	4.090s	136.616us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	39.500s	9.917ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.930s	637.258us	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.690s	100.076us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.251m	35.531ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.251m	35.531ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.251m	35.531ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	39.500s	9.917ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	4.090s	136.616us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.251m	35.531ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	26.410s	2.702ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	39.500s	9.917ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.650s	2.859ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.73738587411841249699682902548857530640476282522606821593329408991965742166272
      Line 109, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2859004634 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2859004634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---