KMAC/UNMASKED Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	34.070s	1.050ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.580s	26.935us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.700s	74.300us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.190s	306.170us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.900s	74.647us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.210s	28.317us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.700s	74.300us	1	1	100.00
		kmac_csr_aliasing	3.900s	74.647us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.720s	53.029us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.660s	75.359us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	4.224m	4.206ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.855m	47.288ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.900s	615.475us	1	1	100.00
		kmac_test_vectors_sha3_256	22.095m	246.559ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.700s	4.744ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.180s	284.351us	1	1	100.00
		kmac_test_vectors_shake_128	2.093m	81.377ms	1	1	100.00
		kmac_test_vectors_shake_256	3.236m	10.850ms	1	1	100.00
		kmac_test_vectors_kmac	2.750s	101.485us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.400s	110.944us	1	1	100.00
V2	sideload	kmac_sideload	3.104m	10.246ms	1	1	100.00
V2	app	kmac_app	1.249m	53.160ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.225m	6.218ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	27.130s	1.351ms	1	1	100.00
V2	error	kmac_error	2.311m	6.863ms	1	1	100.00
V2	key_error	kmac_key_error	5.290s	1.062ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.090s	32.100us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	6.300s	1.603ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	18.090s	1.731ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	38.540s	5.359ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.790s	94.743us	1	1	100.00
V2	stress_all	kmac_stress_all	3.417m	52.163ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.730s	19.947us	1	1	100.00
V2	alert_test	kmac_alert_test	1.660s	55.829us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.630s	183.683us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.630s	183.683us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.580s	26.935us	1	1	100.00
		kmac_csr_rw	1.700s	74.300us	1	1	100.00
		kmac_csr_aliasing	3.900s	74.647us	1	1	100.00
		kmac_same_csr_outstanding	2.410s	73.965us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.580s	26.935us	1	1	100.00
		kmac_csr_rw	1.700s	74.300us	1	1	100.00
		kmac_csr_aliasing	3.900s	74.647us	1	1	100.00
		kmac_same_csr_outstanding	2.410s	73.965us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.120s	222.535us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.120s	222.535us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.120s	222.535us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.120s	222.535us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.910s	185.829us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	38.080s	15.803ms	1	1	100.00
		kmac_tl_intg_err	2.990s	190.742us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.990s	190.742us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.790s	94.743us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	34.070s	1.050ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.104m	10.246ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.120s	222.535us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	38.080s	15.803ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	38.080s	15.803ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	38.080s	15.803ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	34.070s	1.050ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.790s	94.743us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	38.080s	15.803ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.870s	111.956us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	34.070s	1.050ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	34.210s	2.430ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.62064804519483202386425970048485716963174553489352660564428769569005682466041
      Line 126, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2430437359 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2430437359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---