OTBN Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: `b6a2634`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	158.864us	1	1	100.00
V1	single_binary	otbn_single	16.000s	115.107us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	34.799us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	13.474us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	514.207us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	43.946us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	6.000s	66.548us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	13.474us	1	1	100.00
		otbn_csr_aliasing	6.000s	43.946us	1	1	100.00
V1	mem_walk	otbn_mem_walk	28.000s	3.564ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	9.000s	295.838us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	16.000s	61.041us	1	1	100.00
V2	multi_error	otbn_multi_err	40.000s	1.312ms	1	1	100.00
V2	back_to_back	otbn_multi	30.000s	134.769us	1	1	100.00
V2	stress_all	otbn_stress_all	35.000s	532.238us	1	1	100.00
V2	lc_escalation	otbn_escalate	10.000s	32.444us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	17.845us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	14.000s	41.249us	1	1	100.00
V2	alert_test	otbn_alert_test	8.000s	20.664us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	78.902us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	226.535us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	226.535us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	34.799us	1	1	100.00
		otbn_csr_rw	6.000s	13.474us	1	1	100.00
		otbn_csr_aliasing	6.000s	43.946us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	33.885us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	34.799us	1	1	100.00
		otbn_csr_rw	6.000s	13.474us	1	1	100.00
		otbn_csr_aliasing	6.000s	43.946us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	33.885us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	7.000s	68.946us	1	1	100.00
		otbn_dmem_err	8.000s	23.555us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	14.617us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	198.681us	1	1	100.00
		otbn_mac_bignum_acc_err	23.000s	97.287us	1	1	100.00
		otbn_urnd_err	7.000s	23.775us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	16.667us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	18.841us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	42.100us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	8.000s	79.990us	0	1	0.00
		otbn_tl_intg_err	17.000s	101.302us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	14.000s	102.818us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	158.864us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	8.000s	23.555us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	7.000s	68.946us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	17.000s	101.302us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	10.000s	32.444us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	7.000s	68.946us	1	1	100.00
		otbn_dmem_err	8.000s	23.555us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	17.845us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	16.667us	1	1	100.00
		otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	16.000s	115.107us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	7.000s	68.946us	1	1	100.00
		otbn_dmem_err	8.000s	23.555us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	17.845us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	16.667us	1	1	100.00
		otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	10.000s	32.444us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	7.000s	68.946us	1	1	100.00
		otbn_dmem_err	8.000s	23.555us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	17.845us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	16.667us	1	1	100.00
		otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	16.000s	115.107us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	17.000s	76.756us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	20.591us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	39.000s	141.253us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	39.000s	141.253us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	27.054us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	105.318us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	160.790us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	160.790us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	6.000s	25.514us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	16.000s	115.107us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	16.000s	115.107us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	16.000s	115.107us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	30.000s	134.769us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	16.000s	115.107us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	16.000s	115.107us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	30.764us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	16.000s	115.107us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.000s	79.990us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.000m	1.919ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.83090043649648235087908574670310238771558458079433579941896890303222565027229
    Line 437, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1918834210 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1918834210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.35181133061078880107625811750537146911727441038286094215442509076061253672683
Line 104, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 79990038 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 79990038 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  79990038 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  79990038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---