PATTGEN Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	66.397us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	15.014us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	14.848us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	994.096us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	16.340us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	31.496us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	14.848us	1	1	100.00
		pattgen_csr_aliasing	4.000s	16.340us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf			0	1	0.00
V2	cnt_rollover	cnt_rollover	36.000s	1.392ms	1	1	100.00
V2	error	pattgen_error	4.000s	111.509us	1	1	100.00
V2	stress_all	pattgen_stress_all	5.000s	79.715us	0	1	0.00
V2	alert_test	pattgen_alert_test	3.000s	144.802us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	50.136us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	53.093us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	53.093us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	15.014us	1	1	100.00
		pattgen_csr_rw	3.000s	14.848us	1	1	100.00
		pattgen_csr_aliasing	4.000s	16.340us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	12.211us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	15.014us	1	1	100.00
		pattgen_csr_rw	3.000s	14.848us	1	1	100.00
		pattgen_csr_aliasing	4.000s	16.340us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	12.211us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	162.468us	1	1	100.00
		pattgen_sec_cm	4.000s	42.406us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	162.468us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	1.933m	15.979ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	145.076us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.110551684928168388618220490819905185308065271843366047440762629102806084411505
      Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.82436132203881330726793730301626528240041039113627360469659892130689770001685
      Line 129, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4168790143 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 4168817556 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 4168817556 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 4169017556 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.36926687670089861420030373823973164440912443726831220259723681951311323937925
      Line 147, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        UVM_ERROR @  79714762 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
        ------------------------------------
        Name      Type          Size  Value
        ------------------------------------
        exp_item  pattgen_item  -     @10445