RV_TIMER Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.690s	13.644us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.470s	65.900us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.350s	12.373us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.190s	150.071us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.620s	24.730us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.910s	40.577us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.350s	12.373us	1	1	100.00
		rv_timer_csr_aliasing	1.620s	24.730us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.500s	351.531us	1	1	100.00
V2	disabled	rv_timer_disabled	1.530s	32.622us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	9.436m	1.471s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	9.436m	1.471s	1	1	100.00
V2	stress	rv_timer_stress_all	2.410s	4.578ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.710s	17.956us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.490s	14.937us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.060s	168.542us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.060s	168.542us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.470s	65.900us	1	1	100.00
		rv_timer_csr_rw	1.350s	12.373us	1	1	100.00
		rv_timer_csr_aliasing	1.620s	24.730us	1	1	100.00
		rv_timer_same_csr_outstanding	1.690s	30.913us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.470s	65.900us	1	1	100.00
		rv_timer_csr_rw	1.350s	12.373us	1	1	100.00
		rv_timer_csr_aliasing	1.620s	24.730us	1	1	100.00
		rv_timer_same_csr_outstanding	1.690s	30.913us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.800s	786.790us	1	1	100.00
		rv_timer_tl_intg_err	2.200s	717.844us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.200s	717.844us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	27.560s	4.695ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.610s	23.498us	1	1	100.00
		rv_timer_max	1.600s	26.758us	1	1	100.00
		TOTAL			19	19	100.00