SPI_DEVICE/1R1W Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	51.520s	14.145ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.230s	37.139us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.560s	35.172us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.880s	5.794ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.160s	428.144us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.330s	483.772us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.560s	35.172us	1	1	100.00
		spi_device_csr_aliasing	10.160s	428.144us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	2.060s	34.162us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.490s	398.602us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.900s	89.278us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.620s	1.590us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.700s	4.389us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.710s	149.325us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.710s	149.325us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.090s	409.498us	1	1	100.00
		spi_device_tpm_sts_read	1.630s	37.201us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	5.400s	888.627us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.590s	1.241ms	1	1	100.00
		spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.270s	2.297ms	1	1	100.00
		spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.270s	2.297ms	1	1	100.00
		spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.030s	524.213us	1	1	100.00
		spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.030s	524.213us	1	1	100.00
		spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.030s	524.213us	1	1	100.00
		spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.030s	524.213us	1	1	100.00
		spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.030s	524.213us	1	1	100.00
		spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.920s	209.946us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	11.550s	8.092ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	11.550s	8.092ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	11.550s	8.092ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.320s	6.221ms	1	1	100.00
		spi_device_read_buffer_direct	5.640s	331.696us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	11.550s	8.092ms	1	1	100.00
		spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	3.263m	186.693ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.340s	509.213us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.340s	509.213us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	51.520s	14.145ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.917m	33.790ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.430s	69.355us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.720s	23.250us	1	1	100.00
V2	intr_test	spi_device_intr_test	2.140s	32.516us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.780s	59.168us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.780s	59.168us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.230s	37.139us	1	1	100.00
		spi_device_csr_rw	2.560s	35.172us	1	1	100.00
		spi_device_csr_aliasing	10.160s	428.144us	1	1	100.00
		spi_device_same_csr_outstanding	5.060s	599.537us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.230s	37.139us	1	1	100.00
		spi_device_csr_rw	2.560s	35.172us	1	1	100.00
		spi_device_csr_aliasing	10.160s	428.144us	1	1	100.00
		spi_device_same_csr_outstanding	5.060s	599.537us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.320s	369.408us	1	1	100.00
		spi_device_tl_intg_err	14.210s	298.504us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	14.210s	298.504us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.417m	93.739ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.53145349673593593912479159564999973399723689835372177296795200960379223188259
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1070264 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[71])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1070264 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1070264 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[967])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.79994532311385652175685317800025351290336531652997221734725501023385771882106
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3710707 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3710707 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   3807707 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x969ea6 [100101101001111010100110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   3807707 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x969ea6 [100101101001111010100110] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])