SPI_DEVICE/2P Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: `b6a2634`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.304m	17.198ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.750s	22.967us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.290s	34.727us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.760s	1.067ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	9.800s	2.242ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.900s	100.504us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.290s	34.727us	1	1	100.00
		spi_device_csr_aliasing	9.800s	2.242ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	2.010s	54.048us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.820s	25.983us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.760s	140.340us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	2.210s	49.812us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.670s	5.302us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.320s	99.866us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.320s	99.866us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.200s	1.141ms	1	1	100.00
		spi_device_tpm_sts_read	1.980s	345.694us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	28.900s	13.691ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.280s	375.269us	1	1	100.00
		spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.880s	469.557us	1	1	100.00
		spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.880s	469.557us	1	1	100.00
		spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.920s	700.030us	1	1	100.00
		spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.920s	700.030us	1	1	100.00
		spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.920s	700.030us	1	1	100.00
		spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.920s	700.030us	1	1	100.00
		spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.920s	700.030us	1	1	100.00
		spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	8.310s	7.101ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	5.680s	1.954ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	5.680s	1.954ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	5.680s	1.954ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.360s	385.876us	1	1	100.00
		spi_device_read_buffer_direct	5.400s	1.712ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	5.680s	1.954ms	1	1	100.00
		spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	21.530s	1.126ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.690s	110.495us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.690s	110.495us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.304m	17.198ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	21.440s	3.458ms	1	1	100.00
V2	stress_all	spi_device_stress_all	29.160s	80.240ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.720s	14.012us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.940s	17.309us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.840s	1.119ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.840s	1.119ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.750s	22.967us	1	1	100.00
		spi_device_csr_rw	2.290s	34.727us	1	1	100.00
		spi_device_csr_aliasing	9.800s	2.242ms	1	1	100.00
		spi_device_same_csr_outstanding	5.180s	857.810us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.750s	22.967us	1	1	100.00
		spi_device_csr_rw	2.290s	34.727us	1	1	100.00
		spi_device_csr_aliasing	9.800s	2.242ms	1	1	100.00
		spi_device_same_csr_outstanding	5.180s	857.810us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	1.890s	43.928us	1	1	100.00
		spi_device_tl_intg_err	11.520s	7.066ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.520s	7.066ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds			0	1	0.00
		TOTAL			31	33	93.94

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.60933918889197103992461103912832138720793275112001486973533064627611289591249
Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   4443661 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4443661 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
  UVM_ERROR @   4481661 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x69b7b7 [11010011011011110110111] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
  UVM_ERROR @   4481661 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 0.spi_device_flash_mode_ignore_cmds.43265329670182030204123897729438208674774439267430261389661895274262024661936
    Log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```