SRAM_CTRL/RET Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.430s	179.385us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.740s	18.161us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.510s	15.794us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.360s	116.146us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.610s	19.194us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.850s	68.510us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.510s	15.794us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	19.194us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.830s	4.649ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.160s	97.040us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.257m	4.190ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.885m	1.772ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.960s	6.579ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.452m	51.349ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.730s	5.393ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.442m	558.817us	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	10.770s	3.699ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.760m	16.674ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	18.100s	99.539us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	12.410s	365.012us	1	1	100.00
		sram_ctrl_throughput_w_readback	17.300s	185.661us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.996m	2.074ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.840s	80.684us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	47.037m	64.129ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.460s	38.012us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.600s	26.663us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.600s	26.663us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.740s	18.161us	1	1	100.00
		sram_ctrl_csr_rw	1.510s	15.794us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	19.194us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.500s	103.120us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.740s	18.161us	1	1	100.00
		sram_ctrl_csr_rw	1.510s	15.794us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	19.194us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.500s	103.120us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.050s	269.085us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.570s	14.460us	0	1	0.00
		sram_ctrl_tl_intg_err	2.640s	664.604us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.570s	14.460us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.640s	664.604us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.996m	2.074ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.996m	2.074ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.510s	15.794us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.442m	558.817us	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.442m	558.817us	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.442m	558.817us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.730s	5.393ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.800s	25.920us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.050s	269.085us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.740s	29.671us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.430s	179.385us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.430s	179.385us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.442m	558.817us	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.570s	14.460us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.730s	5.393ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.570s	14.460us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.570s	14.460us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.430s	179.385us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.570s	14.460us	0	1	0.00
V2S		TOTAL			2	5	40.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	33.520s	1.721ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.52212107666630380629069078538380523375439196605553116935858933486273988987599
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  29670958 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x17) != exp (0x37)
        UVM_INFO @  29670958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.25402432288859008499252112836478649249959368694687632899014749843201930639205
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  25919668 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  25919668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.15170832516029190422130049665477807561992078287665289581682918900745986888190
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  14459692 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  14459692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---