SYSRST_CTRL Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.740s 2.130ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 4.020s 2.472ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 3.110s 2.424ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.630s 2.517ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 4.710s 6.086ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 5.700s 2.048ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.171m 75.304ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 6.310s 3.048ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.890s 2.106ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 5.700s 2.048ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.310s 3.048ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 20.390s 33.447ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 35.030s 76.552ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 8.270s 3.707ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 8.590s 4.847ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 4.150s 2.518ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.020s 2.220ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 3.510s 3.992ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 6.500s 2.612ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 6.400s 10.818ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.100m 41.181ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 6.400s 8.885ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 5.440s 2.012ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 5.280s 2.015ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.930s 2.174ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.930s 2.174ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 4.710s 6.086ms 1 1 100.00
sysrst_ctrl_csr_rw 5.700s 2.048ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.310s 3.048ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.640s 8.577ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 4.710s 6.086ms 1 1 100.00
sysrst_ctrl_csr_rw 5.700s 2.048ms 1 1 100.00
sysrst_ctrl_csr_aliasing 6.310s 3.048ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.640s 8.577ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 40.630s 22.012ms 1 1 100.00
sysrst_ctrl_tl_intg_err 18.610s 22.301ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 18.610s 22.301ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 4.910s 6.838ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00