UART Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: b6a2634

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.470s	244.267us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.590s	16.620us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.650s	13.651us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.040s	183.549us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.700s	17.376us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.640s	226.161us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.650s	13.651us	1	1	100.00
		uart_csr_aliasing	1.700s	17.376us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	20.170s	21.079ms	1	1	100.00
V2	parity	uart_smoke	2.470s	244.267us	1	1	100.00
		uart_tx_rx	20.170s	21.079ms	1	1	100.00
V2	parity_error	uart_intr	17.970s	33.266ms	1	1	100.00
		uart_rx_parity_err	2.461m	101.429ms	1	1	100.00
V2	watermark	uart_tx_rx	20.170s	21.079ms	1	1	100.00
		uart_intr	17.970s	33.266ms	1	1	100.00
V2	fifo_full	uart_fifo_full	16.590s	35.577ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	32.050s	56.746ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	41.230s	39.053ms	1	1	100.00
V2	rx_frame_err	uart_intr	17.970s	33.266ms	1	1	100.00
V2	rx_break_err	uart_intr	17.970s	33.266ms	1	1	100.00
V2	rx_timeout	uart_intr	17.970s	33.266ms	1	1	100.00
V2	perf	uart_perf	10.306m	16.199ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.800s	751.903us	1	1	100.00
V2	line_loopback	uart_loopback	2.800s	751.903us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	14.420s	15.578ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.870s	2.063ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.420s	1.158ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	19.160s	5.977ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.144m	203.624ms	1	1	100.00
V2	stress_all	uart_stress_all	14.602m	177.366ms	1	1	100.00
V2	alert_test	uart_alert_test	1.620s	24.666us	1	1	100.00
V2	intr_test	uart_intr_test	1.520s	14.802us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.940s	41.145us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.940s	41.145us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.590s	16.620us	1	1	100.00
		uart_csr_rw	1.650s	13.651us	1	1	100.00
		uart_csr_aliasing	1.700s	17.376us	1	1	100.00
		uart_same_csr_outstanding	1.730s	35.548us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.590s	16.620us	1	1	100.00
		uart_csr_rw	1.650s	13.651us	1	1	100.00
		uart_csr_aliasing	1.700s	17.376us	1	1	100.00
		uart_same_csr_outstanding	1.730s	35.548us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.880s	134.443us	1	1	100.00
		uart_tl_intg_err	1.970s	194.990us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.970s	194.990us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	33.150s	3.967ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00