CHIP Simulation Results

Tuesday May 06 2025 18:31:39 UTC

GitHub Revision: `b6a2634`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.772m	2.838ms	1	1	100.00
		chip_sw_example_rom	1.181m	2.400ms	1	1	100.00
		chip_sw_example_manufacturer	2.212m	3.454ms	1	1	100.00
		chip_sw_example_concurrency	2.513m	2.921ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.837m	6.390ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.238m	4.108ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.001m	5.882ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.276h	40.021ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	51.500s	2.879ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.276h	40.021ms	1	1	100.00
		chip_csr_rw	3.238m	4.108ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.450s	183.051us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.165m	4.086ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.165m	4.086ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.165m	4.086ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.077m	4.031ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.077m	4.031ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.828m	4.700ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	4.879m	4.176ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.873m	3.663ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	14.455m	7.895ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	28.203m	12.734ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.003m	4.045ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.015m	4.747ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.015m	4.747ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.057m	3.621ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.456m	3.145ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.004m	3.875ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	14.776m	13.946ms	1	1	100.00
		chip_tap_straps_testunlock0	1.618m	2.542ms	1	1	100.00
		chip_tap_straps_rma	4.679m	5.041ms	1	1	100.00
		chip_tap_straps_prod	12.734m	12.754ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.659m	3.008ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.679m	8.203ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.747m	6.023ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.747m	6.023ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.320m	7.282ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	18.017m	13.729ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.701m	4.167ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.614m	5.905ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.170m	17.625ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.894m	2.809ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.673m	6.129ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.264m	3.337ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.641m	7.698ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.946m	3.328ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.620m	4.928ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.682m	2.993ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.268m	3.245ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	5.141m	6.418ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.860m	4.777ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.183m	2.776ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.860m	4.777ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.947m	2.859ms	1	1	100.00
		chip_sw_aes_smoketest	3.102m	2.583ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.213m	3.016ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.644m	2.446ms	1	1	100.00
		chip_sw_csrng_smoketest	1.852m	2.479ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.283m	4.127ms	1	1	100.00
		chip_sw_gpio_smoketest	2.409m	2.688ms	1	1	100.00
		chip_sw_hmac_smoketest	2.955m	3.039ms	1	1	100.00
		chip_sw_kmac_smoketest	2.799m	2.860ms	1	1	100.00
		chip_sw_otbn_smoketest	14.920m	9.077ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.685m	5.486ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.816m	5.520ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.064m	2.604ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.276m	2.733ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.932m	3.158ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.144m	2.983ms	1	1	100.00
		chip_sw_uart_smoketest	1.756m	2.849ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.592m	2.680ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.061m	4.274ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.989h	60.590ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.641m	15.436ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.532m	6.532ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.639m	3.663ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.973m	3.029ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.823h	52.927ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.901h	56.806ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	58.970s	2.535ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	58.970s	2.535ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.276h	40.021ms	1	1	100.00
		chip_same_csr_outstanding	38.498m	29.536ms	1	1	100.00
		chip_csr_hw_reset	3.837m	6.390ms	1	1	100.00
		chip_csr_rw	3.238m	4.108ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.276h	40.021ms	1	1	100.00
		chip_same_csr_outstanding	38.498m	29.536ms	1	1	100.00
		chip_csr_hw_reset	3.837m	6.390ms	1	1	100.00
		chip_csr_rw	3.238m	4.108ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	41.810s	2.031ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.020s	46.160us	1	1	100.00
		xbar_smoke_large_delays	48.580s	8.036ms	1	1	100.00
		xbar_smoke_slow_rsp	38.550s	4.439ms	1	1	100.00
		xbar_random_zero_delays	26.420s	469.555us	1	1	100.00
		xbar_random_large_delays	58.990s	9.823ms	1	1	100.00
		xbar_random_slow_rsp	57.800s	6.744ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	11.740s	384.731us	1	1	100.00
		xbar_error_and_unmapped_addr	18.870s	301.322us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	41.200s	2.206ms	1	1	100.00
		xbar_error_and_unmapped_addr	18.870s	301.322us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	43.390s	1.606ms	1	1	100.00
		xbar_access_same_device_slow_rsp	8.057m	59.519ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	11.920s	492.811us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.571m	4.189ms	1	1	100.00
		xbar_stress_all_with_error	28.870s	1.278ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.806m	2.892ms	1	1	100.00
		xbar_stress_all_with_reset_error	50.940s	297.897us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.641m	15.436ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.485m	28.746ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.778m	15.432ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.888m	10.916ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.181m	16.238ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.354m	15.561ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.651m	14.883ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.362m	14.713ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.640s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	30.150s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	28.900s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.370s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.870s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	30.720s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	31.390s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	27.510s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	33.000s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	28.550s	10.200us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	27.130s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	31.340s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	27.920s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.630s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	30.000s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.130s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.510s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.570s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.340s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.930s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	27.120s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.280s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	28.040s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	28.140s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.880s	10.200us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.718m	11.193ms	1	1	100.00
		rom_e2e_asm_init_dev	37.938m	15.735ms	1	1	100.00
		rom_e2e_asm_init_prod	37.175m	15.359ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.102m	15.655ms	1	1	100.00
		rom_e2e_asm_init_rma	35.054m	14.515ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	34.632m	15.642ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.101m	14.847ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.522m	15.334ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.345m	15.736ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	43.705m	35.193ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	43.705m	35.193ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.765m	2.923ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.894m	2.809ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.906m	2.978ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.791m	3.294ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	13.807m	8.879ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.377m	3.075ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.378m	6.020ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.871m	5.858ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.783m	5.600ms	1	1	100.00
		chip_plic_all_irqs_10	3.807m	4.085ms	1	1	100.00
		chip_plic_all_irqs_20	6.088m	4.869ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.533m	3.306ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.677m	12.364ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.534m	4.935ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.469m	2.745ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.641m	11.265ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.339m	8.250ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.298m	6.672ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.069m	7.751ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.201h	256.571ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.677m	3.722ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.685m	5.486ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.677m	3.722ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.938m	9.536ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.938m	9.536ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.617m	7.314ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.979m	5.366ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.466m	6.317ms	1	1	100.00
		chip_sw_aes_idle	1.791m	3.294ms	1	1	100.00
		chip_sw_hmac_enc_idle	1.929m	2.561ms	1	1	100.00
		chip_sw_kmac_idle	2.230m	2.543ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.156m	4.147ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.986m	5.085ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.456m	4.360ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.453m	4.722ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.146m	11.143ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.778m	4.271ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.003m	4.299ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.735m	3.704ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.217m	5.123ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.970m	3.939ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.684m	4.401ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.320m	7.282ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.769m	4.963ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.735m	3.704ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.217m	5.123ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.701m	4.167ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.614m	5.905ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.170m	17.625ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.894m	2.809ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.673m	6.129ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.264m	3.337ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.641m	7.698ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.946m	3.328ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.620m	4.928ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.682m	2.993ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.965m	3.041ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.653m	4.934ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.567m	7.211ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.008m	23.986ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.388m	3.042ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.464m	3.428ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	12.864m	10.268ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.774m	3.166ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.462m	4.219ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.772m	23.801ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	29.193m	17.256ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.320m	7.282ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.225m	4.472ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.710m	3.150ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.871m	5.858ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	17.339m	8.250ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.853m	6.661ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.862m	2.709ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.954m	6.840ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.456m	2.649ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	30.151m	12.019ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.996m	2.794ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.417m	6.161ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.996m	2.794ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.853m	6.661ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.909m	2.114ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.884m	24.449ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.563m	5.491ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.614m	5.905ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.939m	3.526ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.701m	4.167ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	56.427m	42.527ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.884m	24.449ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.531m	2.968ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	13.290m	7.466ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.377m	4.306ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	56.427m	42.527ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.377m	4.306ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.377m	4.306ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.377m	4.306ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.377m	4.306ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.871m	5.858ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.312m	5.253ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.014m	5.170ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.557m	5.783ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.557m	5.783ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.580m	2.951ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.264m	3.337ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	1.929m	2.561ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.490m	3.138ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	13.944m	7.645ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.955m	4.296ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.596m	6.037ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.963m	4.400ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.930m	3.898ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	13.290m	7.466ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.641m	7.698ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	19.998m	10.288ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	13.807m	8.879ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	33.065m	12.516ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.162m	2.098ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.619m	3.362ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.946m	3.328ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	13.290m	7.466ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.675m	9.959ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.302m	2.980ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.598m	6.860ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.230m	2.543ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.378m	6.020ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	14.776m	13.946ms	1	1	100.00
		chip_tap_straps_rma	4.679m	5.041ms	1	1	100.00
		chip_tap_straps_prod	12.734m	12.754ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.032m	3.307ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.675m	9.959ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.675m	9.959ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.675m	9.959ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	13.227m	8.806ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.377m	4.306ms	1	1	100.00
		chip_sw_flash_rma_unlocked	56.427m	42.527ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.108m	3.315ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.438m	6.604ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.164m	6.502ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.924m	5.327ms	1	1	100.00
		chip_sw_lc_ctrl_transition	10.675m	9.959ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.290m	7.466ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	6.096m	8.124ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.939m	9.721ms	1	1	100.00
		chip_prim_tl_access	2.312m	5.253ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.769m	4.963ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.778m	4.271ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.003m	4.299ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.735m	3.704ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.217m	5.123ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.970m	3.939ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.684m	4.401ms	1	1	100.00
		chip_tap_straps_dev	14.776m	13.946ms	1	1	100.00
		chip_tap_straps_rma	4.679m	5.041ms	1	1	100.00
		chip_tap_straps_prod	12.734m	12.754ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.889m	16.186ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.502m	3.734ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.675m	2.786ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.755m	3.462ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.205m	4.191ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	22.006m	24.508ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.889m	16.186ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.048h	47.048ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.011h	45.610ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.258m	9.068ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	55.111m	46.090ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	22.006m	24.508ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.251m	2.069ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.163m	2.707ms	1	1	100.00
		rom_volatile_raw_unlock	1.313m	2.574ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	51.539m	16.650ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.170m	17.625ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.466m	6.317ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.466m	6.317ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.466m	6.317ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.830m	4.160ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.675m	9.959ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.884m	24.449ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.830m	4.160ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.290m	7.466ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.331m	5.316ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.102m	2.318ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.884m	24.449ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.830m	4.160ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.290m	7.466ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.331m	5.316ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.102m	2.318ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.675m	9.959ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.793m	4.065ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.032m	3.307ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.108m	3.315ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.438m	6.604ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.164m	6.502ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.924m	5.327ms	1	1	100.00
		chip_sw_lc_ctrl_transition	10.675m	9.959ms	1	1	100.00
		chip_prim_tl_access	2.312m	5.253ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.312m	5.253ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.970m	9.222ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.489m	7.825ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	19.931m	28.430ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.545m	7.800ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.806m	8.499ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	7.708m	6.312ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	16.972m	22.286ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	16.788m	14.363ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.938m	9.536ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.988m	10.220ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.589m	4.637ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.489m	7.825ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.614m	4.307ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	32.067m	37.931ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.919m	7.165ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.965m	4.472ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.852m	26.548ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.091m	7.025ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.487m	9.326ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	20.791m	27.359ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.246m	2.533ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.871m	5.858ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.096m	8.124ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.096m	8.124ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.487m	9.326ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.852m	26.548ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.589m	4.637ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.685m	5.486ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.800m	5.323ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.635m	4.100ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.022m	3.088ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.677m	12.364ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.330m	3.428ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.871m	5.858ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	12.298m	6.672ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.183m	4.800ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.219m	5.081ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.370m	2.716ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.102m	2.318ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.635m	4.100ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.635m	4.100ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	12.387m	13.145ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.983m	13.839ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.800m	5.323ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.427m	4.576ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.037m	6.761ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.679m	5.041ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.889m	16.186ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.783m	5.600ms	1	1	100.00
		chip_plic_all_irqs_10	3.807m	4.085ms	1	1	100.00
		chip_plic_all_irqs_20	6.088m	4.869ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.827m	2.152ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.512m	3.662ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.641m	15.436ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.692m	6.128ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.274m	3.485ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.654m	3.607ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.804m	3.498ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.331m	5.316ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.620m	4.928ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	4.676m	6.140ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	4.359m	5.950ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.939m	9.721ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.871m	5.858ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.747m	6.023ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.091m	7.025ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	15.950m	22.246ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.285m	2.567ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.662m	3.593ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.729m	4.961ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.950m	22.246ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.950m	22.246ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	38.801m	20.450ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	38.801m	20.450ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.241m	4.967ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	43.705m	35.193ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.236m	2.704ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.830m	2.950ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.891m	3.954ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.309m	3.443ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.991m	8.074ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.306h	32.281ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	27.677m	11.990ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	3.021m	3.506ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.500m	2.618ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.339m	2.759ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.385h	71.416ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.741m	5.970ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.839m	10.856ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.493m	11.343ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.920m	11.567ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.057m	3.542ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.893m	3.580ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.740m	3.244ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.709s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.898m	5.081ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.675m	2.671ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	9.973m	4.822ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	13.951m	7.045ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.743m	2.850ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.084m	4.780ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.232m	2.124ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.373m	4.413ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	5.086m	6.684ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.204m	5.712ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.487m	9.326ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.839m	10.856ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.493m	11.343ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.920m	11.567ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.925m	5.047ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.871m	5.858ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.424h	37.810ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.424h	37.810ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.395m	3.216ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.077m	4.031ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	46.682m	18.649ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.186m	2.982ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.949m	5.168ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.712m	3.265ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.707m	2.807ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.531m	3.975ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.089s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.225m	3.466ms	1	1	100.00
		TOTAL			287	325	88.31

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.94879595220542445324656439744367917101983597770275751804863313066734174926
    Line 712, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.30996511058709868095172185331541072112636580757870487286802295601199955397385
    Line 671, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1605356210496106724660556181501760671708895938764867903529842156354846840236
    Line 619, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.48951830464553690342988182851661036207940231047305288146957647238085330481457
    Line 668, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.34873962102085251177797543036181866187153779400030060272390650606841608822809
    Line 643, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.63859066352419950185052794615270901370132601488268889787133535038248702739225
    Line 563, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.66074160923538168153931887755712395133262718725926740508546606130670745639613
    Line 556, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.44598920138208319317173883389865488648152724083803317673832138860024881557210
    Line 488, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.46790806297108806287888373748744345474403073044856886559367016734374031997193
    Line 606, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.8652620443845195879146546914084601890458576694434195097118958562143741721091
    Line 652, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.31090243306200986122963810189903600103937355540699744692949223960738052163719
    Line 716, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.85327896690894083892259080537929901302188448487306727621621026504083759404167
    Line 680, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.114402274656357038888359168565680907594097039119378333567136438851922675852542
    Line 625, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.12192456162411828585562678790688591091390856042878404919476060748548018738588
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.145s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.79929316087915445570907740301242111375136499836866712339945770293412642240395
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.166s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.40929465100454096870346438489848676606197799868727856835752012687180581438172
    Line 782, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.77039417291565595919572597200751717739228649035389336210538314323092002867749
    Line 621, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.24223605029239334213500124958277914932085435233926507140914209806495865553949
    Line 702, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.105220434373400195774370716862436561836238365051225150858472093732932903312311
    Line 604, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.70120581978761184113680383514415098614740660082566176526537298983871728682383
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3484.840176 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3484.840176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@80061) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.20468165956226825910328585155292023192964533679329968702933796403008001342393
Line 439, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4100.355528 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@80061) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4100.355528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.71520016198983919189978918097644781794911461957367755255331851774010028947087
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35192.823821 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35192.823821 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.92026983318511896753476855648460266624797278312358372056635672571650107522474
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3075.096428 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3075.096428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.38176133764585076718985702651153885060779719949315347123053248657997031399783
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2745.164914 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2745.164914 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.27350466755168277960181039063638396428492566210859078909686470086141545911762
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2709.081334 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2709.081334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37453) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.102581645820852866576639998105085622675767861549521874808866918251594393396187
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2535.310352 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37453) { a_addr: 'h107bc  a_data: 'h6a39781a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h18d69  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2535.310352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.91741198374984948323277019515511715611371764930860711001066461280507467621019
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3663.182000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3663.182000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.107708655657854567693170773830214442135030047883210906891001158615051014855168
    Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3028.896000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3028.896000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.109428630097120070053849256416482236560397850052208584520168536891396303578083
    Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 13728.828979 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 13728.828979 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.523838042982837391801385632001502197934585747341644417215985696717484258544
    Line 698, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.16057681529231658128048185334305860634499176927485111903659035729279515439849
    Line 563, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33221) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.92270926834368626961110062084673725717878202436196429197961650664316885925035
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2878.878716 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33221) { a_addr: 'h106c4  a_data: 'h7bbaa1e6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h4  a_user: 'h18a60  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2878.878716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---