ADC_CTRL Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	7.000s	6.051ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.890s	1.189ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.000s	441.333us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	9.750s	27.001ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.730s	1.085ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.870s	502.712us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.000s	441.333us	1	1	100.00
		adc_ctrl_csr_aliasing	3.730s	1.085ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	6.493m	487.519ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	13.534m	502.834ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	3.843m	484.560ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	6.537m	489.225ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	38.770s	350.585ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.214m	200.101ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	10.262m	345.319ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	8.851m	343.741ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	5.360s	4.235ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	15.980s	40.154ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.546m	99.999ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	21.920s	49.475ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.070s	348.069us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.480s	526.941us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.620s	562.747us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.620s	562.747us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.890s	1.189ms	1	1	100.00
		adc_ctrl_csr_rw	3.000s	441.333us	1	1	100.00
		adc_ctrl_csr_aliasing	3.730s	1.085ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.680s	4.280ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.890s	1.189ms	1	1	100.00
		adc_ctrl_csr_rw	3.000s	441.333us	1	1	100.00
		adc_ctrl_csr_aliasing	3.730s	1.085ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.680s	4.280ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	8.310s	4.328ms	1	1	100.00
		adc_ctrl_tl_intg_err	5.140s	4.928ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	5.140s	4.928ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.890s	5.948ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00