EDN Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.990s 59.275us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.730s 14.566us 1 1 100.00
V1 csr_rw edn_csr_rw 2.090s 22.824us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.120s 96.371us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.910s 14.392us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.020s 38.318us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.090s 22.824us 1 1 100.00
edn_csr_aliasing 1.910s 14.392us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.120s 40.801us 1 1 100.00
V2 csrng_commands edn_genbits 2.120s 40.801us 1 1 100.00
V2 genbits edn_genbits 2.120s 40.801us 1 1 100.00
V2 interrupts edn_intr 1.580s 29.124us 1 1 100.00
V2 alerts edn_alert 1.840s 79.390us 1 1 100.00
V2 errs edn_err 1.650s 24.685us 1 1 100.00
V2 disable edn_disable 1.710s 13.233us 1 1 100.00
edn_disable_auto_req_mode 1.750s 99.589us 1 1 100.00
V2 stress_all edn_stress_all 3.330s 260.197us 1 1 100.00
V2 intr_test edn_intr_test 1.640s 53.557us 1 1 100.00
V2 alert_test edn_alert_test 1.740s 53.826us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.230s 91.391us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.230s 91.391us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.730s 14.566us 1 1 100.00
edn_csr_rw 2.090s 22.824us 1 1 100.00
edn_csr_aliasing 1.910s 14.392us 1 1 100.00
edn_same_csr_outstanding 1.960s 50.948us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.730s 14.566us 1 1 100.00
edn_csr_rw 2.090s 22.824us 1 1 100.00
edn_csr_aliasing 1.910s 14.392us 1 1 100.00
edn_same_csr_outstanding 1.960s 50.948us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.930s 2.206ms 1 1 100.00
edn_tl_intg_err 2.160s 48.891us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.760s 114.120us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.840s 79.390us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.930s 2.206ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.930s 2.206ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.930s 2.206ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.930s 2.206ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.840s 79.390us 1 1 100.00
edn_sec_cm 7.930s 2.206ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.840s 79.390us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.160s 48.891us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets