ENTROPY_SRC Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	5.000s	24.007us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	5.000s	92.458us	1	1	100.00
V1	csr_rw	entropy_src_csr_rw	5.000s	49.360us	1	1	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	7.000s	94.066us	1	1	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	6.000s	1.311ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	4.000s	99.766us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	5.000s	49.360us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	1.311ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	entropy_src_smoke	5.000s	24.007us	1	1	100.00
		entropy_src_rng	19.000s	3.227ms	0	1	0.00
		entropy_src_fw_ov	4.917m	16.016ms	1	1	100.00
V2	firmware_mode	entropy_src_fw_ov	4.917m	16.016ms	1	1	100.00
V2	rng_mode	entropy_src_rng	19.000s	3.227ms	0	1	0.00
V2	rng_max_rate	entropy_src_rng_max_rate	1.833m	17.231ms	1	1	100.00
V2	health_checks	entropy_src_rng	19.000s	3.227ms	0	1	0.00
V2	conditioning	entropy_src_rng	19.000s	3.227ms	0	1	0.00
V2	interrupts	entropy_src_rng	19.000s	3.227ms	0	1	0.00
		entropy_src_intr	8.000s	475.239us	1	1	100.00
V2	alerts	entropy_src_rng	19.000s	3.227ms	0	1	0.00
		entropy_src_functional_alerts	6.000s	210.062us	1	1	100.00
V2	stress_all	entropy_src_stress_all	4.283m	13.126ms	1	1	100.00
V2	functional_errors	entropy_src_functional_errors	5.000s	430.433us	1	1	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	13.000s	354.056us	1	1	100.00
V2	intr_test	entropy_src_intr_test	4.000s	13.202us	1	1	100.00
V2	alert_test	entropy_src_alert_test	4.000s	100.908us	1	1	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	6.000s	152.923us	1	1	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	6.000s	152.923us	1	1	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	5.000s	92.458us	1	1	100.00
		entropy_src_csr_rw	5.000s	49.360us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	1.311ms	1	1	100.00
		entropy_src_same_csr_outstanding	5.000s	46.834us	1	1	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	5.000s	92.458us	1	1	100.00
		entropy_src_csr_rw	5.000s	49.360us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	1.311ms	1	1	100.00
		entropy_src_same_csr_outstanding	5.000s	46.834us	1	1	100.00
V2		TOTAL			11	12	91.67
V2S	tl_intg_err	entropy_src_sec_cm	5.000s	174.726us	1	1	100.00
		entropy_src_tl_intg_err	7.000s	228.681us	1	1	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	19.000s	3.227ms	0	1	0.00
		entropy_src_cfg_regwen	5.000s	15.742us	1	1	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	19.000s	3.227ms	0	1	0.00
V2S	sec_cm_config_redun	entropy_src_rng	19.000s	3.227ms	0	1	0.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	19.000s	3.227ms	0	1	0.00
		entropy_src_fw_ov	4.917m	16.016ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	5.000s	430.433us	1	1	100.00
		entropy_src_sec_cm	5.000s	174.726us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	5.000s	430.433us	1	1	100.00
		entropy_src_sec_cm	5.000s	174.726us	1	1	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	19.000s	3.227ms	0	1	0.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	5.000s	430.433us	1	1	100.00
		entropy_src_sec_cm	5.000s	174.726us	1	1	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	5.000s	430.433us	1	1	100.00
		entropy_src_sec_cm	5.000s	174.726us	1	1	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	5.000s	430.433us	1	1	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	6.000s	210.062us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	7.000s	228.681us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	4.000s	6.041us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			20	22	90.91

Failure Buckets

• UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts has 1 failures:

  • Test entropy_src_rng has 1 failures.

    • 0.entropy_src_rng.12578320516783582681578175067712404640161963998304047151268792359318805079452
      Line 620, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng/latest/run.log

        UVM_ERROR @ 3226638035 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: entropy_src_reg_block.recov_alert_sts
        UVM_INFO @ 3226638035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_*/entropy_src_csr_assert_fpv.sv,294): Assertion conf_rd_A has failed has 1 failures:

  • Test entropy_src_rng_with_xht_rsps has 1 failures.

    • 0.entropy_src_rng_with_xht_rsps.91037187106263080894340826973429315629577945352771617590274111328337914925679
      Line 153, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_with_xht_rsps/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,294): (time 6041245 PS) Assertion tb.dut.entropy_src_csr_assert.conf_rd_A has failed
        UVM_ERROR @   6041245 ps: (entropy_src_csr_assert_fpv.sv:294) [ASSERT FAILED] conf_rd_A
        UVM_INFO @   6041245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---