HMAC Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.050s 147.044us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.580s 33.575us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.640s 26.141us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.170s 707.473us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.190s 651.796us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 3.010s 33.429us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.640s 26.141us 1 1 100.00
hmac_csr_aliasing 6.190s 651.796us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 11.450s 4.829ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.125m 3.866ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.430s 191.199us 1 1 100.00
hmac_test_sha384_vectors 19.780s 1.147ms 1 1 100.00
hmac_test_sha512_vectors 6.452m 45.761ms 1 1 100.00
hmac_test_hmac256_vectors 10.450s 377.098us 1 1 100.00
hmac_test_hmac384_vectors 9.850s 353.107us 1 1 100.00
hmac_test_hmac512_vectors 10.430s 339.374us 1 1 100.00
V2 burst_wr hmac_burst_wr 5.180s 234.237us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 12.131m 5.955ms 1 1 100.00
V2 error hmac_error 30.320s 858.632us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.048m 14.817ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.050s 147.044us 1 1 100.00
hmac_long_msg 11.450s 4.829ms 1 1 100.00
hmac_back_pressure 1.125m 3.866ms 1 1 100.00
hmac_datapath_stress 12.131m 5.955ms 1 1 100.00
hmac_burst_wr 5.180s 234.237us 1 1 100.00
hmac_stress_all 11.558m 28.969ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.050s 147.044us 1 1 100.00
hmac_long_msg 11.450s 4.829ms 1 1 100.00
hmac_back_pressure 1.125m 3.866ms 1 1 100.00
hmac_datapath_stress 12.131m 5.955ms 1 1 100.00
hmac_wipe_secret 1.048m 14.817ms 1 1 100.00
hmac_test_sha256_vectors 8.430s 191.199us 1 1 100.00
hmac_test_sha384_vectors 19.780s 1.147ms 1 1 100.00
hmac_test_sha512_vectors 6.452m 45.761ms 1 1 100.00
hmac_test_hmac256_vectors 10.450s 377.098us 1 1 100.00
hmac_test_hmac384_vectors 9.850s 353.107us 1 1 100.00
hmac_test_hmac512_vectors 10.430s 339.374us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.050s 147.044us 1 1 100.00
hmac_long_msg 11.450s 4.829ms 1 1 100.00
hmac_back_pressure 1.125m 3.866ms 1 1 100.00
hmac_datapath_stress 12.131m 5.955ms 1 1 100.00
hmac_burst_wr 5.180s 234.237us 1 1 100.00
hmac_error 30.320s 858.632us 1 1 100.00
hmac_wipe_secret 1.048m 14.817ms 1 1 100.00
hmac_test_sha256_vectors 8.430s 191.199us 1 1 100.00
hmac_test_sha384_vectors 19.780s 1.147ms 1 1 100.00
hmac_test_sha512_vectors 6.452m 45.761ms 1 1 100.00
hmac_test_hmac256_vectors 10.450s 377.098us 1 1 100.00
hmac_test_hmac384_vectors 9.850s 353.107us 1 1 100.00
hmac_test_hmac512_vectors 10.430s 339.374us 1 1 100.00
hmac_stress_all 11.558m 28.969ms 1 1 100.00
V2 stress_all hmac_stress_all 11.558m 28.969ms 1 1 100.00
V2 alert_test hmac_alert_test 1.570s 173.548us 1 1 100.00
V2 intr_test hmac_intr_test 1.540s 50.642us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.700s 275.510us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.700s 275.510us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.580s 33.575us 1 1 100.00
hmac_csr_rw 1.640s 26.141us 1 1 100.00
hmac_csr_aliasing 6.190s 651.796us 1 1 100.00
hmac_same_csr_outstanding 2.540s 192.367us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.580s 33.575us 1 1 100.00
hmac_csr_rw 1.640s 26.141us 1 1 100.00
hmac_csr_aliasing 6.190s 651.796us 1 1 100.00
hmac_same_csr_outstanding 2.540s 192.367us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.840s 224.022us 1 1 100.00
hmac_tl_intg_err 3.220s 159.578us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.220s 159.578us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.050s 147.044us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.260s 435.473us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.343m 8.090ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.920s 123.471us 1 1 100.00
TOTAL 28 28 100.00