I2C Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: `3add6b6`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	17.390s	3.324ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	15.260s	5.527ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.780s	29.267us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.790s	72.817us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.020s	117.797us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.520s	424.236us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.500s	39.662us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.790s	72.817us	1	1	100.00
		i2c_csr_aliasing	2.520s	424.236us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.380s	186.353us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all			0	1	0.00
V2	host_maxperf	i2c_host_perf	11.689m	29.033ms	1	1	100.00
V2	host_override	i2c_host_override	1.520s	42.874us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.788m	2.937ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	24.590s	1.533ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.110s	508.857us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.470s	249.773us	1	1	100.00
		i2c_host_fifo_reset_rx	3.530s	679.854us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.508m	2.360ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	13.050s	779.869us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.140s	294.689us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.690s	3.644ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	6.590m	41.173ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.870s	1.624ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.890s	3.618ms	1	1	100.00
		i2c_target_intr_smoke	5.700s	1.246ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.250s	407.639us	1	1	100.00
		i2c_target_fifo_reset_tx	1.970s	403.685us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.380m	32.351ms	1	1	100.00
		i2c_target_stress_rd	12.890s	3.618ms	1	1	100.00
		i2c_target_intr_stress_wr	1.118m	23.662ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.000s	4.258ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.650s	598.492us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.340s	1.169ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	7.450s	11.019ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.400s	813.932us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.800s	115.776us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	11.689m	29.033ms	1	1	100.00
		i2c_host_perf_precise	2.430s	41.666us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	13.050s	779.869us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.640s	107.972us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.200s	536.722us	1	1	100.00
		i2c_target_nack_acqfull_addr	3.000s	7.346ms	1	1	100.00
		i2c_target_nack_txstretch	2.040s	480.588us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.660s	250.343us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.560s	1.684ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.440s	48.346us	1	1	100.00
V2	intr_test	i2c_intr_test	1.790s	166.436us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.780s	209.378us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.780s	209.378us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.780s	29.267us	1	1	100.00
		i2c_csr_rw	1.790s	72.817us	1	1	100.00
		i2c_csr_aliasing	2.520s	424.236us	1	1	100.00
		i2c_same_csr_outstanding	1.780s	36.263us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.780s	29.267us	1	1	100.00
		i2c_csr_rw	1.790s	72.817us	1	1	100.00
		i2c_csr_aliasing	2.520s	424.236us	1	1	100.00
		i2c_same_csr_outstanding	1.780s	36.263us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.740s	143.535us	1	1	100.00
		i2c_sec_cm	1.640s	790.963us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.740s	143.535us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.160s	1.058ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.850s	194.309us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	18.450s	3.221ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.77477747768615556744278837773360738410930141251061525715006739211277537701774
    Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1057667443 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1057667443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.25316454899104909132377872471309624089368850353923922229635564413238390875612
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3221233660 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3221233660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 0.i2c_host_stress_all.98259899624475153065994103571842709492759737671203568449302495969465918051310
    Log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.98202034242126168305812502037267601295866280863303101475227242892862649095865
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 194309270 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 194309270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.67031709834367781163334064650257833141437478962022513965852314811884361557821
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 11019464675 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 11019464675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.19980210966025690924737628361289170289811789649719591164869357456998735382821
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 294689187 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @16547