KEYMGR Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.960s	106.845us	1	1	100.00
V1	random	keymgr_random	37.700s	7.852ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.920s	47.829us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.080s	31.886us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.600s	257.493us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.110s	379.535us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.910s	114.386us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.080s	31.886us	1	1	100.00
		keymgr_csr_aliasing	6.110s	379.535us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	11.420s	292.971us	1	1	100.00
V2	sideload	keymgr_sideload	2.710s	184.269us	1	1	100.00
		keymgr_sideload_kmac	3.310s	256.443us	1	1	100.00
		keymgr_sideload_aes	5.720s	1.972ms	1	1	100.00
		keymgr_sideload_otbn	3.120s	219.964us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	4.710s	977.414us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.470s	151.220us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.580s	367.969us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	22.950s	2.670ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.990s	496.326us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	7.710s	693.937us	1	1	100.00
V2	stress_all	keymgr_stress_all	24.480s	935.964us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.860s	25.670us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.810s	26.318us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.460s	186.989us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.460s	186.989us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.920s	47.829us	1	1	100.00
		keymgr_csr_rw	2.080s	31.886us	1	1	100.00
		keymgr_csr_aliasing	6.110s	379.535us	1	1	100.00
		keymgr_same_csr_outstanding	2.050s	31.230us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.920s	47.829us	1	1	100.00
		keymgr_csr_rw	2.080s	31.886us	1	1	100.00
		keymgr_csr_aliasing	6.110s	379.535us	1	1	100.00
		keymgr_same_csr_outstanding	2.050s	31.230us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
		keymgr_tl_intg_err	4.150s	110.870us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.800s	146.478us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.800s	146.478us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.800s	146.478us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.800s	146.478us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	3.930s	279.941us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.150s	110.870us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.800s	146.478us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	11.420s	292.971us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	37.700s	7.852ms	1	1	100.00
		keymgr_csr_rw	2.080s	31.886us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	37.700s	7.852ms	1	1	100.00
		keymgr_csr_rw	2.080s	31.886us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	37.700s	7.852ms	1	1	100.00
		keymgr_csr_rw	2.080s	31.886us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.470s	151.220us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.990s	496.326us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.990s	496.326us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	37.700s	7.852ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	11.930s	1.907ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.510s	1.094ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.470s	151.220us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.510s	1.094ms	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.510s	1.094ms	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.510s	1.094ms	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.440s	1.009ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.510s	1.094ms	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	9.250s	939.913us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.89604364158141047735050537579515008810411452663856830445691086869522021136558
      Line 1087, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 939913016 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 939913016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---